From 5b7767f646ec52b5cddff7254778f75222205af3 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Fri, 21 Oct 2016 23:02:31 +0000
Subject: [PATCH] [x86] add test for missing vector SRA combine via
 computeKnownBits

llvm-svn: 284896
---
 llvm/test/CodeGen/X86/combine-sra.ll | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/llvm/test/CodeGen/X86/combine-sra.ll b/llvm/test/CodeGen/X86/combine-sra.ll
index bfa5b9e98b11..99051d554f46 100644
--- a/llvm/test/CodeGen/X86/combine-sra.ll
+++ b/llvm/test/CodeGen/X86/combine-sra.ll
@@ -296,3 +296,21 @@ define <4 x i32> @combine_vec_ashr_positive(<4 x i32> %x, <4 x i32> %y) {
   %2 = ashr <4 x i32> %1, %y
   ret <4 x i32> %2
 }
+
+define <4 x i32> @combine_vec_ashr_positive_splat(<4 x i32> %x, <4 x i32> %y) {
+; SSE-LABEL: combine_vec_ashr_positive_splat:
+; SSE:       # BB#0:
+; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
+; SSE-NEXT:    psrld $10, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_ashr_positive_splat:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm1
+; AVX-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpsrld $10, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %1 = and <4 x i32> %x, <i32 1023, i32 1023, i32 1023, i32 1023>
+  %2 = ashr <4 x i32> %1, <i32 10, i32 10, i32 10, i32 10>
+  ret <4 x i32> %2
+}