forked from OSchip/llvm-project
x86 FP atomic codegen: don't drop globals, stack
Summary: x86 codegen is clever about generating good code for relaxed floating-point operations, but it was being silly when globals and immediates were involved, forgetting where the global was and loading/storing from/to the wrong place. The same applied to hard-coded address immediates. Don't let it forget about the displacement. This fixes https://llvm.org/bugs/show_bug.cgi?id=25171 A very similar bug when doing floating-points atomics to the stack is also fixed by this patch. This fixes https://llvm.org/bugs/show_bug.cgi?id=25144 Reviewers: pete Subscribers: llvm-commits, majnemer, rsmith Differential Revision: http://reviews.llvm.org/D13749 llvm-svn: 250429
This commit is contained in:
JF Bastien
parent
2811b04874
commit
5b327712b0
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@ -21105,21 +21105,26 @@ X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
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const X86InstrInfo *TII = Subtarget->getInstrInfo();
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DebugLoc DL = MI->getDebugLoc();
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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unsigned MSrc = MI->getOperand(0).getReg();
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MachineOperand MSrc = MI->getOperand(0);
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unsigned VSrc = MI->getOperand(5).getReg();
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const MachineOperand &Disp = MI->getOperand(3);
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MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
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bool hasDisp = Disp.isGlobal() || Disp.isImm();
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if (hasDisp && MSrc.isReg())
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MSrc.setIsKill(false);
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MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
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.addReg(/*Base=*/MSrc)
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.addOperand(/*Base=*/MSrc)
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.addImm(/*Scale=*/1)
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.addReg(/*Index=*/0)
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.addImm(0)
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.addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
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.addReg(0);
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MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
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MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
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.addReg(VSrc)
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.addReg(/*Base=*/MSrc)
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.addOperand(/*Base=*/MSrc)
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.addImm(/*Scale=*/1)
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.addReg(/*Index=*/0)
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.addImm(/*Disp=*/0)
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.addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
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.addReg(/*Segment=*/0);
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MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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@ -871,3 +871,111 @@ define void @fadd_64r(double* %loc, double %val) {
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store atomic i64 %3, i64* %floc release, align 8
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ret void
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}
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@glob32 = global float 0.000000e+00, align 4
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@glob64 = global double 0.000000e+00, align 8
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; Floating-point add to a global using an immediate.
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define void @fadd_32g() {
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; X64-LABEL: fadd_32g:
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; X64-NOT: lock
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; X64: movss .{{[A-Z0-9_]+}}(%rip), %[[XMM:xmm[0-9]+]]
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; X64-NEXT: addss glob32(%rip), %[[XMM]]
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; X64-NEXT: movss %[[XMM]], glob32(%rip)
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; X32-LABEL: fadd_32g:
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; Don't check x86-32 (see comment above).
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%i = load atomic i32, i32* bitcast (float* @glob32 to i32*) monotonic, align 4
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%f = bitcast i32 %i to float
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%add = fadd float %f, 1.000000e+00
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%s = bitcast float %add to i32
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store atomic i32 %s, i32* bitcast (float* @glob32 to i32*) monotonic, align 4
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ret void
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}
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define void @fadd_64g() {
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; X64-LABEL: fadd_64g:
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; X64-NOT: lock
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; X64: movsd .{{[A-Z0-9_]+}}(%rip), %[[XMM:xmm[0-9]+]]
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; X64-NEXT: addsd glob64(%rip), %[[XMM]]
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; X64-NEXT: movsd %[[XMM]], glob64(%rip)
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; X32-LABEL: fadd_64g:
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; Don't check x86-32 (see comment above).
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%i = load atomic i64, i64* bitcast (double* @glob64 to i64*) monotonic, align 8
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%f = bitcast i64 %i to double
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%add = fadd double %f, 1.000000e+00
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%s = bitcast double %add to i64
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store atomic i64 %s, i64* bitcast (double* @glob64 to i64*) monotonic, align 8
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ret void
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}
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; Floating-point add to a hard-coded immediate location using an immediate.
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define void @fadd_32imm() {
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; X64-LABEL: fadd_32imm:
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; X64-NOT: lock
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; X64: movl $3735928559, %e[[M:[a-z]+]]
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; X64: movss .{{[A-Z0-9_]+}}(%rip), %[[XMM:xmm[0-9]+]]
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; X64-NEXT: addss (%r[[M]]), %[[XMM]]
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; X64-NEXT: movss %[[XMM]], (%r[[M]])
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; X32-LABEL: fadd_32imm:
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; Don't check x86-32 (see comment above).
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%i = load atomic i32, i32* inttoptr (i32 3735928559 to i32*) monotonic, align 4
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%f = bitcast i32 %i to float
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%add = fadd float %f, 1.000000e+00
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%s = bitcast float %add to i32
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store atomic i32 %s, i32* inttoptr (i32 3735928559 to i32*) monotonic, align 4
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ret void
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}
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define void @fadd_64imm() {
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; X64-LABEL: fadd_64imm:
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; X64-NOT: lock
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; X64: movl $3735928559, %e[[M:[a-z]+]]
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; X64: movsd .{{[A-Z0-9_]+}}(%rip), %[[XMM:xmm[0-9]+]]
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; X64-NEXT: addsd (%r[[M]]), %[[XMM]]
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; X64-NEXT: movsd %[[XMM]], (%r[[M]])
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; X32-LABEL: fadd_64imm:
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; Don't check x86-32 (see comment above).
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%i = load atomic i64, i64* inttoptr (i64 3735928559 to i64*) monotonic, align 8
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%f = bitcast i64 %i to double
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%add = fadd double %f, 1.000000e+00
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%s = bitcast double %add to i64
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store atomic i64 %s, i64* inttoptr (i64 3735928559 to i64*) monotonic, align 8
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ret void
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}
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; Floating-point add to a stack location.
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define void @fadd_32stack() {
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; X64-LABEL: fadd_32stack:
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; X64-NOT: lock
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; X64: movss .{{[A-Z0-9_]+}}(%rip), %[[XMM:xmm[0-9]+]]
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; X64-NEXT: addss [[STACKOFF:-?[0-9]+]](%rsp), %[[XMM]]
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; X64-NEXT: movss %[[XMM]], [[STACKOFF]](%rsp)
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; X32-LABEL: fadd_32stack:
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; Don't check x86-32 (see comment above).
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%ptr = alloca i32, align 4
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%bc3 = bitcast i32* %ptr to float*
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%load = load atomic i32, i32* %ptr acquire, align 4
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%bc0 = bitcast i32 %load to float
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%fadd = fadd float 1.000000e+00, %bc0
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%bc1 = bitcast float %fadd to i32
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store atomic i32 %bc1, i32* %ptr release, align 4
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ret void
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}
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define void @fadd_64stack() {
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; X64-LABEL: fadd_64stack:
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; X64-NOT: lock
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; X64: movsd .{{[A-Z0-9_]+}}(%rip), %[[XMM:xmm[0-9]+]]
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; X64-NEXT: addsd [[STACKOFF:-?[0-9]+]](%rsp), %[[XMM]]
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; X64-NEXT: movsd %[[XMM]], [[STACKOFF]](%rsp)
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; X32-LABEL: fadd_64stack:
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; Don't check x86-32 (see comment above).
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%ptr = alloca i64, align 8
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%bc3 = bitcast i64* %ptr to double*
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%load = load atomic i64, i64* %ptr acquire, align 8
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%bc0 = bitcast i64 %load to double
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%fadd = fadd double 1.000000e+00, %bc0
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%bc1 = bitcast double %fadd to i64
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store atomic i64 %bc1, i64* %ptr release, align 8
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ret void
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}
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