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[X86] AMD Zen 3: MOVSX32rr32 is a zero-cycle move 

It measures as such, and the reference docs agree.

I can't easily add a MCA test, because there's no mnemonic for it,
it can only be disassembled or created as a MCInst.
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Roman Lebedev 2021-05-07 19:36:37 +03:00
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commit 5b1610a250
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llvm/lib/Target/X86/X86ScheduleZnver3.td
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@ -1466,7 +1466,7 @@ def : IsOptimizableRegisterMove<[
// GPR variants.
MOV32rr, MOV32rr_REV,
MOV64rr, MOV64rr_REV,
// FIXME: MOVSXD32rr, but it is only supported in disassembler.
MOVSX32rr32,
// FIXME: XCHG32rr/XCHG64rr after MCA is fixed
// MMX variants.