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[AArch64] Allow folding FMUL/FADD into FMA for FP16 types 

isFMAFasterThanFMulAndFAdd should return true for FP16 types when
HasFullFP16 is present, since we have the instructions to handle it for
both SVE and NEON. (SVE patterns and tests will follow).

Differential Revision: https://reviews.llvm.org/D96599
This commit is contained in:
Bradley Smith 2021-02-12 12:51:10 +00:00
parent 1dfb06d0b4
commit 5b094bfeb3
2 changed files with 23 additions and 2 deletions
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2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -11569,6 +11569,8 @@ bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(
return false;
switch (VT.getSimpleVT().SimpleTy) {
case MVT::f16:
return Subtarget->hasFullFP16();
case MVT::f32:
case MVT::f64:
return true;

23
llvm/test/CodeGen/AArch64/f16-instructions.ll
View File

@ -62,6 +62,26 @@ define half @test_fmul(half %a, half %b) #0 {
ret half %r
}
; CHECK-CVT-LABEL: test_fmadd:
; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fmul s0, s0, s1
; CHECK-CVT-NEXT: fcvt h0, s0
; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcvt s1, h2
; CHECK-CVT-NEXT: fadd s0, s0, s1
; CHECK-CVT-NEXT: fcvt h0, s0
; CHECK-CVT-NEXT: ret
; CHECK-FP16-LABEL: test_fmadd:
; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
; CHECK-FP16-NEXT: ret
define half @test_fmadd(half %a, half %b, half %c) #0 {
%mul = fmul fast half %a, %b
%r = fadd fast half %mul, %c
ret half %r
}
; CHECK-CVT-LABEL: test_fdiv:
; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s0, h0
@ -1305,8 +1325,7 @@ define half @test_round(half %a) #0 {
; CHECK-CVT-NEXT: ret
; CHECK-FP16-LABEL: test_fmuladd:
; CHECK-FP16-NEXT: fmul h0, h0, h1
; CHECK-FP16-NEXT: fadd h0, h0, h2
; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
; CHECK-FP16-NEXT: ret
define half @test_fmuladd(half %a, half %b, half %c) #0 {