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[AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions. 

Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker

Reviewed By: fhahn, samparker

Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41899

llvm-svn: 322481
This commit is contained in:
Sander de Smalen 2018-01-15 12:47:17 +00:00
parent 0faecf0c33
commit 5aa809db79
2 changed files with 22 additions and 44 deletions
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16
llvm/lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -193,6 +193,7 @@ def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
def SImm10s8Operand : AsmOperandClass {
let Name = "SImm10s8";
let DiagnosticType = "InvalidMemoryIndexedSImm10";
let PredicateMethod = "isSImmScaled<10, 8>";
}
//===----------------------------------------------------------------------===//
@ -221,19 +222,23 @@ def adrlabel : Operand<i64> {
let ParserMatchClass = AdrOperand;
}
class SImmOperand<int width> : AsmOperandClass {
let Name = "SImm" # width;
let DiagnosticType = "InvalidMemoryIndexedSImm" # width;
let RenderMethod = "addImmOperands";
let PredicateMethod = "isSImm<" # width # ">";
}
def simm10Scaled : Operand<i64> {
let ParserMatchClass = SImm10s8Operand;
let DecoderMethod = "DecodeSImm<10>";
let PrintMethod = "printImmScale<8>";
}
// simm9 predicate - True if the immediate is in the range [-256, 255].
def SImm9Operand : AsmOperandClass {
let Name = "SImm9";
let DiagnosticType = "InvalidMemoryIndexedSImm9";
}
def SImm9Operand : SImmOperand<9>;
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
let ParserMatchClass = SImm9Operand;
let DecoderMethod = "DecodeSImm<9>";
}
// simm7sN predicate - True if the immediate is a multiple of N in the range
@ -241,6 +246,7 @@ def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
class SImm7Scaled<int Scale> : AsmOperandClass {
let Name = "SImm7s" # Scale;
let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
let PredicateMethod = "isSImmScaled<7, " # Scale # ">";
}
def SImm7s4Operand : SImm7Scaled<4>;

50
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -470,50 +470,22 @@ public:
bool isImm() const override { return Kind == k_Immediate; }
bool isMem() const override { return false; }
bool isSImm9() const {
template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
template <int Bits, int Scale> bool isSImmScaled() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
int64_t Shift = Bits - 1;
int64_t MinVal = (int64_t(1) << Shift) * -Scale;
int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
int64_t Val = MCE->getValue();
return (Val >= -256 && Val < 256);
}
bool isSImm10s8() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
int64_t Val = MCE->getValue();
return (Val >= -4096 && Val < 4089 && (Val & 7) == 0);
}
bool isSImm7s4() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
int64_t Val = MCE->getValue();
return (Val >= -256 && Val <= 252 && (Val & 3) == 0);
}
bool isSImm7s8() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
int64_t Val = MCE->getValue();
return (Val >= -512 && Val <= 504 && (Val & 7) == 0);
}
bool isSImm7s16() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return false;
int64_t Val = MCE->getValue();
return (Val >= -1024 && Val <= 1008 && (Val & 15) == 0);
return Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0;
}
bool isSymbolicUImm12Offset(const MCExpr *Expr, unsigned Scale) const {
@ -1081,7 +1053,7 @@ public:
// ambiguity in the matcher.
template<int Width>
bool isSImm9OffsetFB() const {
return isSImm9() && !isUImm12Offset<Width / 8>();
return isSImm<9>() && !isUImm12Offset<Width / 8>();
}
bool isAdrpLabel() const {