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[DAG] SimplifyDemandedVectorElts - remove KnownZero/KnownUndef from DCI helper wrapper 

None of the external users actual touch these (they're purely used internally down the recursive call) - its trivial to add another wrapper if anything ever does want to track known elements.
This commit is contained in:
Simon Pilgrim 2022-02-02 11:40:27 +00:00
parent d919d027ba
commit 5aa2acc86b
4 changed files with 13 additions and 38 deletions
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1
llvm/include/llvm/CodeGen/TargetLowering.h
View File

@ -3539,7 +3539,6 @@ public:
/// Helper wrapper around SimplifyDemandedVectorElts.
/// Adds Op back to the worklist upon success.
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
APInt &KnownUndef, APInt &KnownZero,
DAGCombinerInfo &DCI) const;
/// Determine which of the bits specified in Mask are known to be either zero

3
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -2370,13 +2370,12 @@ bool TargetLowering::SimplifyDemandedBits(
bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
const APInt &DemandedElts,
APInt &KnownUndef,
APInt &KnownZero,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
!DCI.isBeforeLegalizeOps());
APInt KnownUndef, KnownZero;
bool Simplified =
SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
if (Simplified) {

11
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -17060,13 +17060,10 @@ static SDValue PerformVMOVNCombine(SDNode *N,
IsTop ? Op1DemandedElts
: APInt::getSplat(NumElts, APInt::getHighBitsSet(2, 1));
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
return SDValue(N, 0);
if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(Op1, Op1DemandedElts, DCI))
return SDValue(N, 0);
return SDValue();
@ -17082,10 +17079,8 @@ static SDValue PerformVQMOVNCombine(SDNode *N,
APInt::getSplat(NumElts, IsTop ? APInt::getLowBitsSet(2, 1)
: APInt::getHighBitsSet(2, 1));
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, DCI))
return SDValue(N, 0);
return SDValue();
}

36
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -40016,10 +40016,8 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
// Simplify source operands based on shuffle mask.
// TODO - merge this into combineX86ShufflesRecursively.
APInt KnownUndef, KnownZero;
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
DCI))
if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, DCI))
return SDValue(N, 0);
// Canonicalize SHUFFLE(BINOP(X,Y)) -> BINOP(SHUFFLE(X),SHUFFLE(Y)).
@ -46034,11 +46032,9 @@ static SDValue combineVectorShiftVar(SDNode *N, SelectionDAG &DAG,
EltBits[0].getZExtValue(), DAG);
}
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
return SDValue(N, 0);
return SDValue();
@ -46915,9 +46911,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
DemandedElts.setBit(I);
}
APInt KnownUndef, KnownZero;
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, KnownUndef,
KnownZero, DCI) ||
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI) ||
TLI.SimplifyDemandedBits(OtherOp, DemandedBits, DemandedElts, DCI);
};
if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) {
@ -47389,9 +47383,7 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
if (!EltBits[I].isAllOnes())
DemandedElts.setBit(I);
APInt KnownUndef, KnownZero;
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, KnownUndef,
KnownZero, DCI);
return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI);
};
if (SimplifyUndemandedElts(N0, N1) || SimplifyUndemandedElts(N1, N0)) {
if (N->getOpcode() != ISD::DELETED_NODE)
@ -48531,10 +48523,8 @@ static SDValue combineVEXTRACT_STORE(SDNode *N, SelectionDAG &DAG,
unsigned StElts = MemVT.getSizeInBits() / VT.getScalarSizeInBits();
APInt DemandedElts = APInt::getLowBitsSet(VT.getVectorNumElements(), StElts);
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, KnownUndef,
KnownZero, DCI)) {
if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, DCI)) {
if (N->getOpcode() != ISD::DELETED_NODE)
DCI.AddToWorklist(N);
return SDValue(N, 0);
@ -50074,10 +50064,8 @@ static SDValue combineX86INT_TO_FP(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt KnownUndef, KnownZero;
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
return SDValue(N, 0);
// Convert a full vector load into vzload when not all bits are needed.
@ -50191,11 +50179,9 @@ static SDValue combineCVTPH2PS(SDNode *N, SelectionDAG &DAG,
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
if (N->getValueType(0) == MVT::v4f32 && Src.getValueType() == MVT::v8i16) {
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedElts = APInt::getLowBitsSet(8, 4);
if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, KnownZero,
DCI)) {
if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, DCI)) {
if (N->getOpcode() != ISD::DELETED_NODE)
DCI.AddToWorklist(N);
return SDValue(N, 0);
@ -53476,11 +53462,9 @@ static SDValue combineVPMADD(SDNode *N, SelectionDAG &DAG,
ISD::isBuildVectorAllZeros(RHS.getNode()))
return DAG.getConstant(0, SDLoc(N), VT);
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
return SDValue(N, 0);
return SDValue();
@ -53549,11 +53533,9 @@ static SDValue combineKSHIFT(SDNode *N, SelectionDAG &DAG,
if (ISD::isBuildVectorAllZeros(N->getOperand(0).getNode()))
return DAG.getConstant(0, SDLoc(N), VT);
APInt KnownUndef, KnownZero;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements());
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
KnownZero, DCI))
if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI))
return SDValue(N, 0);
return SDValue();