forked from OSchip/llvm-project
Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
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@ -3415,13 +3415,15 @@ cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
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}
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((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
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((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
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((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
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// If we have a three-operand form, use that, else the second source operand
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// is just the destination operand again.
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if (Operands.size() == 6)
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((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
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else
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Inst.addOperand(Inst.getOperand(0));
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// If we have a three-operand form, make sure to set Rn to be the operand
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// that isn't the same as Rd.
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unsigned RegOp = 4;
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if (Operands.size() == 6 &&
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((ARMOperand*)Operands[4])->getReg() ==
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((ARMOperand*)Operands[3])->getReg())
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RegOp = 5;
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((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
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Inst.addOperand(Inst.getOperand(0));
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((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
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return true;
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@ -372,9 +372,11 @@ _func:
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@ MUL
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@------------------------------------------------------------------------------
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muls r1, r2, r1
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muls r2, r2, r3
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muls r3, r4
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@ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
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@ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43]
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@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
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