From 5a59b24bdd3b1836884d5792a527b84c6a74b148 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Tue, 19 Jul 2016 19:48:36 +0000
Subject: [PATCH] [GlobalISel] Mark newly-created gvregs as having a bank.

Also verify that we never try to set the size of a vreg associated
to a register class.

Report an error when we encounter that in MIR. Fix a testcase that
hit that error and had a size for no reason.

llvm-svn: 276012
---
 llvm/lib/CodeGen/MIRParser/MIParser.cpp       |  6 ++++-
 llvm/lib/CodeGen/MachineRegisterInfo.cpp      |  7 +++--
 .../MIR/X86/generic-instr-type-error.mir      |  4 +--
 .../unexpected-size-non-generic-register.mir  | 26 +++++++++++++++++++
 4 files changed, 38 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir

diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index b3fd16f15889..8937ee81c6a3 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -973,14 +973,18 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
       TiedDefIdx = Idx;
     }
   } else if (consumeIfPresent(MIToken::lparen)) {
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+
     // Virtual registers may have a size with GlobalISel.
     if (!TargetRegisterInfo::isVirtualRegister(Reg))
       return error("unexpected size on physical register");
+    if (MRI.getRegClassOrRegBank(Reg).is<const TargetRegisterClass *>())
+      return error("unexpected size on non-generic virtual register");
+
     unsigned Size;
     if (parseSize(Size))
       return true;
 
-    MachineRegisterInfo &MRI = MF.getRegInfo();
     MRI.setSize(Reg, Size);
   } else if (PFS.GenericVRegs.count(Reg)) {
     // Generic virtual registers must have a size.
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 613598dbe215..96786552e9b4 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -114,6 +114,9 @@ MachineRegisterInfo::getSize(unsigned VReg) const {
 }
 
 void MachineRegisterInfo::setSize(unsigned VReg, unsigned Size) {
+  // Check that VReg doesn't have a class.
+  assert(!getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>() &&
+         "Can't set the size of a non-generic virtual register");
   getVRegToSize()[VReg] = Size;
 }
 
@@ -124,8 +127,8 @@ MachineRegisterInfo::createGenericVirtualRegister(unsigned Size) {
   // New virtual register number.
   unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
   VRegInfo.grow(Reg);
-  // FIXME: Should we use a dummy register class?
-  VRegInfo[Reg].first = static_cast<TargetRegisterClass *>(nullptr);
+  // FIXME: Should we use a dummy register bank?
+  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
   getVRegToSize()[Reg] = Size;
   RegAllocHints.grow(Reg);
   if (TheDelegate)
diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
index 1f196919afa0..7e5cf47008f1 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
@@ -10,6 +10,6 @@ registers:
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK: [[@LINE+1]]:20: expected a sized type
-    %0(32) = G_ADD %opaque %edi, %edi
+    ; CHECK: [[@LINE+1]]:16: expected a sized type
+    %0 = G_ADD %opaque %edi, %edi
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
new file mode 100644
index 000000000000..981fa2179d4f
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
@@ -0,0 +1,26 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when a register operand is sized
+# but isn't generic.
+
+---
+name:            test_size_regclass
+isSSA:           true
+registers:
+  - { id: 0, class: gr32 }
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: [[@LINE+1]]:8: unexpected size on non-generic virtual register
+    %0(32) = G_ADD i32 %edi, %edi
+...
+
+---
+name:            test_size_physreg
+isSSA:           true
+registers:
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: [[@LINE+1]]:10: unexpected size on physical register
+    %edi(32) = G_ADD i32 %edi, %edi
+...