forked from OSchip/llvm-project
[CVP] Add tests for non-overflowing mulo; NFC
Should be simplified to simple mul. llvm-svn: 358517
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@ -11,10 +11,14 @@ declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
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declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
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declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
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declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
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declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
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declare void @llvm.trap()
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@ -497,6 +501,82 @@ cond.end: ; preds = %cond.false, %entry
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ret i32 %cond
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}
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define i32 @unsigned_mul(i32 %x) {
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; CHECK-LABEL: @unsigned_mul(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], 10000
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; CHECK-NEXT: br i1 [[CMP]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[MULO:%.*]] = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[X]], i32 100)
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; CHECK-NEXT: [[RES:%.*]] = extractvalue { i32, i1 } [[MULO]], 0
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; CHECK-NEXT: [[OV:%.*]] = extractvalue { i32, i1 } [[MULO]], 1
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; CHECK-NEXT: br i1 [[OV]], label [[TRAP:%.*]], label [[COND_END]]
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; CHECK: trap:
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; CHECK-NEXT: tail call void @llvm.trap()
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; CHECK-NEXT: unreachable
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RES]], [[COND_FALSE]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp = icmp ugt i32 %x, 10000
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br i1 %cmp, label %cond.end, label %cond.false
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cond.false: ; preds = %entry
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%mulo = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 100)
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%res = extractvalue { i32, i1 } %mulo, 0
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%ov = extractvalue { i32, i1 } %mulo, 1
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br i1 %ov, label %trap, label %cond.end
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trap: ; preds = %cond.false
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tail call void @llvm.trap()
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unreachable
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cond.end: ; preds = %cond.false, %entry
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%cond = phi i32 [ 0, %entry ], [ %res, %cond.false ]
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ret i32 %cond
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}
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define i32 @signed_mul(i32 %x) {
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; CHECK-LABEL: @signed_mul(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X:%.*]], 10000
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; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], -10000
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; CHECK-NEXT: [[CMP3:%.*]] = or i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: br i1 [[CMP3]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]
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; CHECK: cond.false:
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; CHECK-NEXT: [[MULO:%.*]] = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 [[X]], i32 100)
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; CHECK-NEXT: [[RES:%.*]] = extractvalue { i32, i1 } [[MULO]], 0
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; CHECK-NEXT: [[OV:%.*]] = extractvalue { i32, i1 } [[MULO]], 1
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; CHECK-NEXT: br i1 [[OV]], label [[TRAP:%.*]], label [[COND_END]]
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; CHECK: trap:
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; CHECK-NEXT: tail call void @llvm.trap()
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; CHECK-NEXT: unreachable
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; CHECK: cond.end:
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; CHECK-NEXT: [[COND:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RES]], [[COND_FALSE]] ]
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; CHECK-NEXT: ret i32 [[COND]]
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;
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entry:
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%cmp1 = icmp sgt i32 %x, 10000
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%cmp2 = icmp slt i32 %x, -10000
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%cmp3 = or i1 %cmp1, %cmp2
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br i1 %cmp3, label %cond.end, label %cond.false
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cond.false: ; preds = %entry
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%mulo = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %x, i32 100)
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%res = extractvalue { i32, i1 } %mulo, 0
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%ov = extractvalue { i32, i1 } %mulo, 1
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br i1 %ov, label %trap, label %cond.end
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trap: ; preds = %cond.false
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tail call void @llvm.trap()
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unreachable
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cond.end: ; preds = %cond.false, %entry
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%cond = phi i32 [ 0, %entry ], [ %res, %cond.false ]
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ret i32 %cond
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}
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declare i32 @bar(i32)
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define void @unsigned_loop(i32 %i) {
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