forked from OSchip/llvm-project
GlobalISel: Handle zext(sext x) in artifact combiner
This eliminates the illegal intermediate s8 value in the added test.
This commit is contained in:
Matt Arsenault
parent
968cba8e89
commit
5a0b1472c0
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@ -105,19 +105,23 @@ public:
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Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
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Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
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// zext(trunc x) - > and (aext/copy/trunc x), mask
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// zext(trunc x) - > and (aext/copy/trunc x), mask
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// zext(sext x) -> and (sext x), mask
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Register TruncSrc;
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Register TruncSrc;
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if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
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Register SextSrc;
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if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc))) ||
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mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) {
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LLT DstTy = MRI.getType(DstReg);
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LLT DstTy = MRI.getType(DstReg);
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if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
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if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
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isConstantUnsupported(DstTy))
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isConstantUnsupported(DstTy))
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return false;
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return false;
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LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
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LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
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LLT SrcTy = MRI.getType(SrcReg);
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LLT SrcTy = MRI.getType(SrcReg);
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APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
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APInt MaskVal = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
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auto MIBMask = Builder.buildConstant(
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auto Mask = Builder.buildConstant(
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DstTy, Mask.zext(DstTy.getScalarSizeInBits()));
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DstTy, MaskVal.zext(DstTy.getScalarSizeInBits()));
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Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),
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auto Extended = SextSrc ? Builder.buildSExtOrTrunc(DstTy, SextSrc) :
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MIBMask);
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Builder.buildAnyExtOrTrunc(DstTy, TruncSrc);
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Builder.buildAnd(DstReg, Extended, Mask);
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markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
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markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
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return true;
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return true;
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}
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}
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@ -117,3 +117,165 @@ body: |
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%4:_(s128) = G_ZEXT %3
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%4:_(s128) = G_ZEXT %3
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %4
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...
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...
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---
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name: test_zext_s8_to_s32_of_sext_s1_to_s8
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_zext_s8_to_s32_of_sext_s1_to_s8
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(eq), %0, %1
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%3:_(s8) = G_SEXT %2
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%4:_(s32) = G_ZEXT %3
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$vgpr0 = COPY %4
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...
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---
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name: test_zext_s8_to_s32_of_sext_s1_to_s16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_zext_s8_to_s32_of_sext_s1_to_s16
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_ICMP intpred(eq), %0, %1
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%3:_(s16) = G_SEXT %2
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%4:_(s32) = G_ZEXT %3
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$vgpr0 = COPY %4
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...
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---
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name: test_zext_s8_to_s32_of_sext_s8_to_s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_zext_s8_to_s32_of_sext_s8_to_s16
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; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 1, addrspace 1)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND]](s32)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
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%2:_(s16) = G_SEXT %1
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%3:_(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s8
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; CHECK-LABEL: name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s8
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s32), [[UV2]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[UV3]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
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; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
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; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
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%2:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1
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%3:_(<2 x s8>) = G_SEXT %2
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%4:_(<2 x s32>) = G_ZEXT %3
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$vgpr0_vgpr1 = COPY %4
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...
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---
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name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; CHECK-LABEL: name: test_zext_v2s8_to_v2s32_of_sext_v2s1_to_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s32), [[UV2]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[UV3]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
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; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
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; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
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%2:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1
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%3:_(<2 x s16>) = G_SEXT %2
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%4:_(<2 x s32>) = G_ZEXT %3
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$vgpr0_vgpr1 = COPY %4
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...
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---
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name: test_zext_v2s8_to_v2s32_of_sext_v2s8_to_v2s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_zext_v2s8_to_v2s32_of_sext_v2s8_to_v2s16
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; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 2, addrspace 1)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
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; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(<2 x s8>) = G_LOAD %0 :: (load 2, addrspace 1)
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%2:_(<2 x s16>) = G_SEXT %1
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%3:_(<2 x s32>) = G_ZEXT %2
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$vgpr0_vgpr1 = COPY %3
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...
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