forked from OSchip/llvm-project
[PowerPC] Implement more fusion types for Power10
This implements the rest of Power10 instruction fusion pairs, according to user manual, including 'wide immediate', 'load compare', 'zero move' and 'SHA3 assist'. Only 'SHA3 assist' is enabled by default. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D112912
This commit is contained in:
Qiu Chaofan
parent
8ea3e70fb0
commit
59f4b3d308
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@ -203,6 +203,22 @@ def FeatureLogicalFusion :
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SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
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"Target supports Logical Operations fusion",
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[FeatureFusion]>;
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def FeatureSha3Fusion :
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SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
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"Target supports SHA3 assist fusion",
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[FeatureFusion]>;
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def FeatureCompareFusion:
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SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
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"Target supports Comparison Operations fusion",
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[FeatureFusion]>;
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def FeatureWideImmFusion:
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SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
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"Target supports Wide-Immediate fusion",
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[FeatureFusion]>;
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def FeatureZeroMoveFusion:
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SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
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"Target supports move to SPR with branch fusion",
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[FeatureFusion]>;
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def FeatureUnalignedFloats :
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SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
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"true", "CPU does not trap on unaligned FP access">;
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@ -393,7 +409,7 @@ def ProcessorFeatures {
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// still exist with the exception of those we know are Power9 specific.
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list<SubtargetFeature> FusionFeatures = [
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FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,
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FeatureLogicalFusion, FeatureArithAddFusion
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FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,
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];
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list<SubtargetFeature> P10AdditionalFeatures =
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!listconcat(FusionFeatures, [
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@ -149,6 +149,79 @@ static bool checkOpConstraints(FusionFeature::FusionKind Kd,
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case FusionFeature::FK_SldiAdd:
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return (matchingImmOps(FirstMI, 2, 3) && matchingImmOps(FirstMI, 3, 60)) ||
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(matchingImmOps(FirstMI, 2, 6) && matchingImmOps(FirstMI, 3, 57));
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// rldicl rx, ra, 1, 0 - xor
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case FusionFeature::FK_RotateLeftXor:
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return matchingImmOps(FirstMI, 2, 1) && matchingImmOps(FirstMI, 3, 0);
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// rldicr rx, ra, 1, 63 - xor
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case FusionFeature::FK_RotateRightXor:
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return matchingImmOps(FirstMI, 2, 1) && matchingImmOps(FirstMI, 3, 63);
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// We actually use CMPW* and CMPD*, 'l' doesn't exist as an operand in instr.
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// { lbz,lbzx,lhz,lhzx,lwz,lwzx } - cmpi 0,1,rx,{ 0,1,-1 }
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// { lbz,lbzx,lhz,lhzx,lwz,lwzx } - cmpli 0,L,rx,{ 0,1 }
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case FusionFeature::FK_LoadCmp1:
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// { ld,ldx } - cmpi 0,1,rx,{ 0,1,-1 }
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// { ld,ldx } - cmpli 0,1,rx,{ 0,1 }
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case FusionFeature::FK_LoadCmp2: {
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const MachineOperand &BT = SecondMI.getOperand(0);
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if (!BT.isReg() ||
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(!Register::isVirtualRegister(BT.getReg()) && BT.getReg() != PPC::CR0))
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return false;
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if (SecondMI.getOpcode() == PPC::CMPDI &&
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matchingImmOps(SecondMI, 2, -1, 16))
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return true;
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return matchingImmOps(SecondMI, 2, 0) || matchingImmOps(SecondMI, 2, 1);
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}
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// { lha,lhax,lwa,lwax } - cmpi 0,L,rx,{ 0,1,-1 }
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case FusionFeature::FK_LoadCmp3: {
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const MachineOperand &BT = SecondMI.getOperand(0);
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if (!BT.isReg() ||
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(!Register::isVirtualRegister(BT.getReg()) && BT.getReg() != PPC::CR0))
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return false;
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return matchingImmOps(SecondMI, 2, 0) || matchingImmOps(SecondMI, 2, 1) ||
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matchingImmOps(SecondMI, 2, -1, 16);
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}
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// mtctr - { bcctr,bcctrl }
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case FusionFeature::FK_ZeroMoveCTR:
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// ( mtctr rx ) is alias of ( mtspr 9, rx )
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return (FirstMI.getOpcode() != PPC::MTSPR &&
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FirstMI.getOpcode() != PPC::MTSPR8) ||
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matchingImmOps(FirstMI, 0, 9);
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// mtlr - { bclr,bclrl }
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case FusionFeature::FK_ZeroMoveLR:
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// ( mtlr rx ) is alias of ( mtspr 8, rx )
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return (FirstMI.getOpcode() != PPC::MTSPR &&
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FirstMI.getOpcode() != PPC::MTSPR8) ||
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matchingImmOps(FirstMI, 0, 8);
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// addis rx,ra,si - addi rt,rx,SI, SI >= 0
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case FusionFeature::FK_AddisAddi: {
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const MachineOperand &RA = FirstMI.getOperand(1);
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const MachineOperand &SI = SecondMI.getOperand(2);
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if (!SI.isImm() || !RA.isReg())
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return false;
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if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8)
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return false;
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return SignExtend64(SI.getImm(), 16) >= 0;
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}
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// addi rx,ra,si - addis rt,rx,SI, ra > 0, SI >= 2
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case FusionFeature::FK_AddiAddis: {
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const MachineOperand &RA = FirstMI.getOperand(1);
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const MachineOperand &SI = FirstMI.getOperand(2);
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if (!SI.isImm() || !RA.isReg())
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return false;
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if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8)
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return false;
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int64_t ExtendedSI = SignExtend64(SI.getImm(), 16);
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return ExtendedSI >= 2;
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}
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}
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llvm_unreachable("All the cases should have been handled");
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@ -78,5 +78,80 @@ FUSION_FEATURE(VecLogical, hasLogicalFusion, -1,
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FUSION_FEATURE(SldiAdd, hasArithAddFusion, -1, FUSION_OP_SET(RLDICR, RLDICR_32),
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FUSION_OP_SET(ADD4, ADD8, SUBF, SUBF8))
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// rldicl rx, ra, 1, 0 - xor
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FUSION_FEATURE(RotateLeftXor, hasSha3Fusion, 1,
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FUSION_OP_SET(RLDICL, RLDICL_32, RLDICL_32_64),
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FUSION_OP_SET(XOR, XOR8))
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// rldicr rx, ra, 1, 63 - xor
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FUSION_FEATURE(RotateRightXor, hasSha3Fusion, 1,
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FUSION_OP_SET(RLDICR, RLDICR_32), FUSION_OP_SET(XOR, XOR8))
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// There're two special cases in 'load-compare' series, so we have to split
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// them into several pattern groups to fit into current framework. This can
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// be clearer once we switched to a more expressive approach.
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// { lbz,lbzx,lhz,lhzx,lwz,lwzx } - cmpi 0,1,rx,{ 0,1,-1 }
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// { lbz,lbzx,lhz,lhzx,lwz,lwzx } - cmpli 0,L,rx,{ 0,1 }
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FUSION_FEATURE(LoadCmp1, hasCompareFusion, 1,
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FUSION_OP_SET(LBZ, LBZ8, LBZX, LBZX8, LBZXTLS, LBZXTLS_,
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LBZXTLS_32, LHZ, LHZ8, LHZX, LHZX8, LHZXTLS,
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LHZXTLS_, LHZXTLS_32, LWZ, LWZ8, LWZX, LWZX8,
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LWZXTLS, LWZXTLS_, LWZXTLS_32),
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FUSION_OP_SET(CMPDI, CMPLDI, CMPLWI))
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// { ld,ldx } - cmpi 0,1,rx,{ 0,1,-1 }
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// { ld,ldx } - cmpli 0,1,rx,{ 0,1 }
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FUSION_FEATURE(LoadCmp2, hasCompareFusion, 1,
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FUSION_OP_SET(LD, LDX, LDXTLS, LDXTLS_),
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FUSION_OP_SET(CMPDI, CMPLDI))
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// { lha,lhax,lwa,lwax } - cmpi 0,L,rx,{ 0,1,-1 }
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FUSION_FEATURE(LoadCmp3, hasCompareFusion, 1,
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FUSION_OP_SET(LHA, LHA8, LHAX, LHAX8, LWA, LWA_32, LWAX,
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LWAX_32),
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FUSION_OP_SET(CMPLDI, CMPLWI))
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// ori - oris
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FUSION_FEATURE(OriOris, hasWideImmFusion, 1, FUSION_OP_SET(ORI, ORI8),
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FUSION_OP_SET(ORIS, ORIS8))
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// lis - ori
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FUSION_FEATURE(LisOri, hasWideImmFusion, 1, FUSION_OP_SET(LIS, LIS8),
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FUSION_OP_SET(ORI, ORI8))
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// oris - ori
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FUSION_FEATURE(OrisOri, hasWideImmFusion, 1, FUSION_OP_SET(ORIS, ORIS8),
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FUSION_OP_SET(ORI, ORI8))
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// xori - xoris
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FUSION_FEATURE(XoriXoris, hasWideImmFusion, 1, FUSION_OP_SET(XORI, XORI8),
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FUSION_OP_SET(XORIS, XORIS8))
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// xoris - xori
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FUSION_FEATURE(XorisXori, hasWideImmFusion, 1, FUSION_OP_SET(XORIS, XORIS8),
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FUSION_OP_SET(XORI, XORI8))
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// addis rx,ra,si - addi rt,rx,SI, SI >= 0
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FUSION_FEATURE(AddisAddi, hasWideImmFusion, 1,
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FUSION_OP_SET(ADDIS, ADDIS8, ADDIStocHA8),
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FUSION_OP_SET(ADDI, ADDI8, ADDItocL))
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// addi rx,ra,si - addis rt,rx,SI, ra > 0, SI >= 2
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FUSION_FEATURE(AddiAddis, hasWideImmFusion, 1,
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FUSION_OP_SET(ADDI, ADDI8, ADDItocL),
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FUSION_OP_SET(ADDIS, ADDIS8, ADDIStocHA8))
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// mtctr - { bcctr,bcctrl }
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FUSION_FEATURE(ZeroMoveCTR, hasZeroMoveFusion, -1,
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FUSION_OP_SET(MTCTR, MTCTRloop, MTSPR8, MTSPR),
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FUSION_OP_SET(BCCTR, BCCTRn, BCCTR8, BCCTR8n, BCCTRL, BCCTRLn,
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BCCTRL8, BCCTRL8n, gBCCTR, gBCCTRL))
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// mtlr - { bclr,bclrl }
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FUSION_FEATURE(ZeroMoveLR, hasZeroMoveFusion, -1,
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FUSION_OP_SET(MTLR8, MTLR, MTSPR8, MTSPR),
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FUSION_OP_SET(BCLR, BCLRn, gBCLR, BCLRL, BCLRLn, gBCLRL))
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#undef FUSION_FEATURE
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#undef FUSION_OP_SET
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@ -131,6 +131,10 @@ void PPCSubtarget::initializeEnvironment() {
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HasAddLogicalFusion = false;
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HasLogicalAddFusion = false;
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HasLogicalFusion = false;
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HasSha3Fusion = false;
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HasCompareFusion = false;
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HasWideImmFusion = false;
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HasZeroMoveFusion = false;
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IsISA2_06 = false;
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IsISA2_07 = false;
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IsISA3_0 = false;
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@ -151,6 +151,10 @@ protected:
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bool HasAddLogicalFusion;
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bool HasLogicalAddFusion;
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bool HasLogicalFusion;
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bool HasSha3Fusion;
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bool HasCompareFusion;
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bool HasWideImmFusion;
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bool HasZeroMoveFusion;
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bool IsISA2_06;
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bool IsISA2_07;
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bool IsISA3_0;
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@ -340,6 +344,10 @@ public:
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bool hasAddLogicalFusion() const { return HasAddLogicalFusion; }
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bool hasLogicalAddFusion() const { return HasLogicalAddFusion; }
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bool hasLogicalFusion() const { return HasLogicalFusion; }
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bool hasCompareFusion() const { return HasCompareFusion; }
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bool hasWideImmFusion() const { return HasWideImmFusion; }
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bool hasSha3Fusion() const { return HasSha3Fusion; }
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bool hasZeroMoveFusion() const { return HasZeroMoveFusion; }
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bool needsSwapsForVSXMemOps() const {
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return hasVSX() && isLittleEndian() && !hasP9Vector();
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}
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@ -1,6 +1,7 @@
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# REQUIRES: asserts
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# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 -x=mir < %s \
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# RUN: -debug-only=machine-scheduler -start-before=postmisched 2>&1 \
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# RUN: -mattr=+fuse-zeromove,+fuse-cmp,+fuse-wideimm \
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# RUN: | FileCheck %s
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# CHECK: add_mulld:%bb.0
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@ -93,3 +94,55 @@ body: |
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renamable $x3 = ADD8 killed renamable $x4, $x5
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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# CHECK: rldicl_xor:%bb.0
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# CHECK: Macro fuse: SU(0) - SU(1) / RLDICL - XOR8
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---
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name: rldicl_xor
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3, $x4, $x5
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renamable $x4 = RLDICL $x3, 1, 0
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renamable $x3 = XOR8 killed renamable $x4, $x5
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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# CHECK: rldicr_xor:%bb.0
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# CHECK: Macro fuse: SU(0) - SU(1) / RLDICR - XOR8
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---
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name: rldicr_xor
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3, $x4, $x5
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renamable $x4 = RLDICR $x3, 1, 63
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renamable $x3 = XOR8 killed renamable $x4, $x5
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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# CHECK: ori_oris:%bb.0
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# CHECK: Macro fuse: SU(0) - SU(1) / ORI8 - ORIS8
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---
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name: ori_oris
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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renamable $x4 = ORI8 $x3, 63
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renamable $x3 = ORIS8 killed renamable $x4, 20
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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# CHECK: load_cmp:%bb.0
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# CHECK: Macro fuse: SU(0) - SU(1) / LD - CMPDI
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---
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name: load_cmp
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x3, $x4, $x5
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renamable $x3 = LD 0, killed renamable $x3
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renamable $cr0 = CMPDI killed renamable $x3, 0
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renamable $x3 = ISEL8 killed renamable $x5, killed renamable $x4, renamable $cr0lt, implicit killed $cr0
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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