forked from OSchip/llvm-project
[AVR] Implement non-constant bit rotations
This lets us do bit rotations of variable amount. llvm-svn: 301794
This commit is contained in:
Dylan McKay
parent
4064dc76c5
commit
59e7fe3da8
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@ -79,6 +79,11 @@ AVRTargetLowering::AVRTargetLowering(AVRTargetMachine &tm)
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setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::ROTL, MVT::i8, Custom);
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setOperationAction(ISD::ROTL, MVT::i16, Custom);
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setOperationAction(ISD::ROTR, MVT::i8, Custom);
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setOperationAction(ISD::ROTR, MVT::i16, Custom);
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setOperationAction(ISD::BR_CC, MVT::i8, Custom);
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setOperationAction(ISD::BR_CC, MVT::i16, Custom);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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@ -273,6 +278,12 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SRL:
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return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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case ISD::ROTL:
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return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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case ISD::ROTR:
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return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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case ISD::SRA:
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return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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@ -1440,6 +1451,22 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
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Opc = AVR::LSRWRd;
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RC = &AVR::DREGSRegClass;
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break;
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case AVR::Rol8:
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Opc = AVR::ROLRd;
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RC = &AVR::GPR8RegClass;
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break;
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case AVR::Rol16:
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Opc = AVR::ROLWRd;
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RC = &AVR::DREGSRegClass;
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break;
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case AVR::Ror8:
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Opc = AVR::RORRd;
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RC = &AVR::GPR8RegClass;
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break;
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case AVR::Ror16:
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Opc = AVR::RORWRd;
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RC = &AVR::DREGSRegClass;
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break;
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}
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -1552,6 +1579,10 @@ AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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case AVR::Lsl16:
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case AVR::Lsr8:
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case AVR::Lsr16:
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case AVR::Rol8:
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case AVR::Rol16:
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case AVR::Ror8:
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case AVR::Ror16:
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case AVR::Asr8:
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case AVR::Asr16:
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return insertShift(MI, MBB);
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@ -43,6 +43,8 @@ enum NodeType {
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ROL, ///< Bit rotate left.
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LSLLOOP, ///< A loop of single logical shift left instructions.
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LSRLOOP, ///< A loop of single logical shift right instructions.
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ROLLOOP, ///< A loop of single left bit rotate instructions.
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RORLOOP, ///< A loop of single right bit rotate instructions.
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ASRLOOP, ///< A loop of single arithmetic shift right instructions.
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/// AVR conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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@ -64,6 +64,8 @@ def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>;
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// Pseudo shift nodes for non-constant shift amounts.
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def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>;
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def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>;
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def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>;
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def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>;
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def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>;
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//===----------------------------------------------------------------------===//
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@ -1932,7 +1934,6 @@ def Lsr8 : ShiftPseudo<
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[(set i8:$dst, (AVRlsrLoop i8:$src, i8:$cnt))]
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>;
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def Lsr16 : ShiftPseudo<
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(outs DREGS:$dst),
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(ins DREGS:$src, GPR8:$cnt),
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@ -1940,6 +1941,34 @@ def Lsr16 : ShiftPseudo<
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[(set i16:$dst, (AVRlsrLoop i16:$src, i8:$cnt))]
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>;
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def Rol8 : ShiftPseudo<
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(outs GPR8:$dst),
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(ins GPR8:$src, GPR8:$cnt),
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"# Rol8 PSEUDO",
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[(set i8:$dst, (AVRrolLoop i8:$src, i8:$cnt))]
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>;
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def Rol16 : ShiftPseudo<
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(outs DREGS:$dst),
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(ins DREGS:$src, GPR8:$cnt),
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"# Rol16 PSEUDO",
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[(set i16:$dst, (AVRrolLoop i16:$src, i8:$cnt))]
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>;
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def Ror8 : ShiftPseudo<
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(outs GPR8:$dst),
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(ins GPR8:$src, GPR8:$cnt),
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"# Ror8 PSEUDO",
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[(set i8:$dst, (AVRrorLoop i8:$src, i8:$cnt))]
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>;
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def Ror16 : ShiftPseudo<
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(outs DREGS:$dst),
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(ins DREGS:$src, GPR8:$cnt),
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"# Ror16 PSEUDO",
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[(set i16:$dst, (AVRrorLoop i16:$src, i8:$cnt))]
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>;
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def Asr8 : ShiftPseudo<
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(outs GPR8:$dst),
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(ins GPR8:$src, GPR8:$cnt),
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@ -0,0 +1,55 @@
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; RUN: llc < %s -march=avr | FileCheck %s
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; Bit rotation tests.
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; CHECK-LABEL: rol8:
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define i8 @rol8(i8 %val, i8 %amt) {
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; CHECK: andi r22, 7
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; CHECK-NEXT: cp r22, r0
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; CHECK-NEXT: breq LBB0_2
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; CHECK-NEXT: LBB0_1:
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; CHECK-NEXT: rol r24
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; CHECK-NEXT: subi r22, 1
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; CHECK-NEXT: brne LBB0_1
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; CHECK-NEXT:LBB0_2:
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; CHECK-NEXT: ret
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%mod = urem i8 %amt, 8
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%inv = sub i8 8, %mod
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%parta = shl i8 %val, %mod
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%partb = lshr i8 %val, %inv
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%rotl = or i8 %parta, %partb
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ret i8 %rotl
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}
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; CHECK-LABEL: ror8:
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define i8 @ror8(i8 %val, i8 %amt) {
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; CHECK: andi r22, 7
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; CHECK-NEXT: cp r22, r0
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; CHECK-NEXT: breq LBB1_2
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; CHECK-NEXT: LBB1_1:
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: subi r22, 1
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; CHECK-NEXT: brne LBB1_1
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; CHECK-NEXT:LBB1_2:
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; CHECK-NEXT: ret
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%mod = urem i8 %amt, 8
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%inv = sub i8 8, %mod
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%parta = lshr i8 %val, %mod
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%partb = shl i8 %val, %inv
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%rotr = or i8 %parta, %partb
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ret i8 %rotr
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}
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