forked from OSchip/llvm-project
parent
79d9a93a71
commit
59d9e9126d
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@ -48,32 +48,6 @@ struct SparcV9InstrInfo : public TargetInstrInfo {
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return -1;
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return -1;
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}
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}
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
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///
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MachineInstr* createNOPinstr() const {
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return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcV9IntRegClass::g0);
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}
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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bool isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `sethi g0, 0'
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if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isImmediate() && op0.getImmedValue() == 0 &&
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op1.getType() == MachineOperand::MO_MachineRegister &&
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op1.getMachineRegNum() == SparcV9IntRegClass::g0)
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{
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return true;
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}
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}
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return false;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const
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virtual bool hasResultInterlock(MachineOpCode opCode) const
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{
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// All UltraSPARC instructions have interlocks (note that delay slots
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