forked from OSchip/llvm-project
[mips] Fix TAILCALL's operand node type.
llvm-svn: 166341
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@ -598,9 +598,10 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
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IIAlu>;
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// Jump
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class JumpFJ<bits<6> op, string instr_asm, SDPatternOperator operator>:
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FJ<op, (outs), (ins jmptarget:$target), !strconcat(instr_asm, "\t$target"),
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[(operator bb:$target)], IIBranch> {
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class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
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SDPatternOperator operator, SDPatternOperator targetoperator>:
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FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"),
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[(operator targetoperator:$target)], IIBranch> {
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let isTerminator=1;
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let isBarrier=1;
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let hasDelaySlot = 1;
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@ -1003,7 +1004,7 @@ def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
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}
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/// Jump and Branch Instructions
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def J : JumpFJ<0x02, "j", br>,
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def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
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Requires<[RelocStatic, HasStandardEncoding]>, IsBranch;
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def JR : IndirectBranch<CPURegs>;
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def B : UncondBranch<0x04, "b">;
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@ -1022,7 +1023,7 @@ def JAL : JumpLink<0x03, "jal">;
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def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
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def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
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def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
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def TAILCALL : JumpFJ<0x02, "j", br>, IsTailCall;
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def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall;
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def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
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def RET : RetBase<CPURegs>;
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@ -1133,6 +1134,11 @@ def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
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//def : MipsPat<(MipsJmpLink CPURegs:$dst),
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// (JALR CPURegs:$dst)>;
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// Tail call
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL tglobaladdr:$dst)>;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL texternalsym:$dst)>;
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// hi/lo relocs
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def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
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def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
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