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[Target] Use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2021-11-22 08:21:07 -08:00
parent 02298c15d5
commit 59a26448a6
14 changed files with 42 additions and 70 deletions
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17
llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
View File

@ -706,9 +706,7 @@ bool AMDGPUCFGStructurizer::prepare() {
// Remove unconditional branch instr.
// Add dummy exit block iff there are multiple returns.
for (SmallVectorImpl<MachineBasicBlock *>::const_iterator
It = OrderedBlks.begin(), E = OrderedBlks.end(); It != E; ++It) {
MachineBasicBlock *MBB = *It;
for (MachineBasicBlock *MBB : OrderedBlks) {
removeUnconditionalBranch(MBB);
removeRedundantConditionalBranch(MBB);
if (isReturnBlock(MBB)) {
@ -851,14 +849,10 @@ bool AMDGPUCFGStructurizer::run() {
void AMDGPUCFGStructurizer::orderBlocks(MachineFunction *MF) {
int SccNum = 0;
MachineBasicBlock *MBB;
for (scc_iterator<MachineFunction *> It = scc_begin(MF); !It.isAtEnd();
++It, ++SccNum) {
const std::vector<MachineBasicBlock *> &SccNext = *It;
for (std::vector<MachineBasicBlock *>::const_iterator
blockIter = SccNext.begin(), blockEnd = SccNext.end();
blockIter != blockEnd; ++blockIter) {
MBB = *blockIter;
for (MachineBasicBlock *MBB : SccNext) {
OrderedBlks.push_back(MBB);
recordSccnum(MBB, SccNum);
}
@ -1601,11 +1595,8 @@ void AMDGPUCFGStructurizer::addDummyExitBlock(
FuncRep->push_back(DummyExitBlk); //insert to function
insertInstrEnd(DummyExitBlk, R600::RETURN);
for (SmallVectorImpl<MachineBasicBlock *>::iterator It = RetMBB.begin(),
E = RetMBB.end(); It != E; ++It) {
MachineBasicBlock *MBB = *It;
MachineInstr *MI = getReturnInstr(MBB);
if (MI)
for (MachineBasicBlock *MBB : RetMBB) {
if (MachineInstr *MI = getReturnInstr(MBB))
MI->eraseFromParent();
MBB->addSuccessor(DummyExitBlk);
LLVM_DEBUG(dbgs() << "Add dummyExitBlock to BB" << MBB->getNumber()

4
llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp
View File

@ -177,9 +177,7 @@ bool R600ClauseMergePass::runOnMachineFunction(MachineFunction &MF) {
const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
TII = ST.getInstrInfo();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
MachineBasicBlock::iterator LatestCFAlu = E;
while (I != E) {

4
llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
View File

@ -301,9 +301,7 @@ public:
const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
TII = ST.getInstrInfo();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::iterator I = MBB.begin();
if (I != MBB.end() && I->getOpcode() == R600::CF_ALU)
continue; // BB was already parsed

4
llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
View File

@ -73,9 +73,7 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
const R600RegisterInfo &TRI = TII->getRegisterInfo();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::iterator I = MBB.begin();
while (I != MBB.end()) {
MachineInstr &MI = *I;

6
llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
View File

@ -323,14 +323,12 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
TII = ST.getInstrInfo();
MRI = &Fn.getRegInfo();
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
MachineBasicBlock *MB = &*MBB;
for (MachineBasicBlock &MB : Fn) {
PreviousRegSeq.clear();
PreviousRegSeqByReg.clear();
PreviousRegSeqByUndefCount.clear();
for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
for (MachineBasicBlock::iterator MII = MB.begin(), MIIE = MB.end();
MII != MIIE; ++MII) {
MachineInstr &MI = *MII;
if (MI.getOpcode() != R600::REG_SEQUENCE) {

11
llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
View File

@ -291,20 +291,19 @@ bool SIPreEmitPeephole::mustRetainExeczBranch(
MBBI != End && MBBI != ToI; ++MBBI) {
const MachineBasicBlock &MBB = *MBBI;
for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
for (const MachineInstr &MI : MBB) {
// When a uniform loop is inside non-uniform control flow, the branch
// leaving the loop might never be taken when EXEC = 0.
// Hence we should retain cbranch out of the loop lest it become infinite.
if (I->isConditionalBranch())
if (MI.isConditionalBranch())
return true;
if (TII->hasUnwantedEffectsWhenEXECEmpty(*I))
if (TII->hasUnwantedEffectsWhenEXECEmpty(MI))
return true;
// These instructions are potentially expensive even if EXEC = 0.
if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) ||
TII->isDS(*I) || I->getOpcode() == AMDGPU::S_WAITCNT)
if (TII->isSMRD(MI) || TII->isVMEM(MI) || TII->isFLAT(MI) ||
TII->isDS(MI) || MI.getOpcode() == AMDGPU::S_WAITCNT)
return true;
++NumInstr;

9
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
View File

@ -484,14 +484,13 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
IsConst64Disabled = true;
// Traverse basic blocks.
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
++BI) {
for (MachineBasicBlock &MBB : MF) {
PotentiallyNewifiableTFR.clear();
findPotentialNewifiableTFRs(*BI);
findPotentialNewifiableTFRs(MBB);
// Traverse instructions in basic block.
for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
MI != End;) {
for (MachineBasicBlock::iterator MI = MBB.begin(), End = MBB.end();
MI != End;) {
MachineInstr &I1 = *MI++;
if (I1.isDebugInstr())

7
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
View File

@ -942,12 +942,11 @@ void HexagonGenInsert::collectInBlock(MachineBasicBlock *B,
// can remove them from the list of available registers once all DT
// successors have been processed.
RegisterSet BlockDefs, InsDefs;
for (MachineBasicBlock::iterator I = B->begin(), E = B->end(); I != E; ++I) {
MachineInstr *MI = &*I;
for (MachineInstr &MI : *B) {
InsDefs.clear();
getInstrDefs(MI, InsDefs);
getInstrDefs(&MI, InsDefs);
// Leave those alone. They are more transparent than "insert".
bool Skip = MI->isCopy() || MI->isRegSequence();
bool Skip = MI.isCopy() || MI.isRegSequence();
if (!Skip) {
// Visit all defined registers, and attempt to find the corresponding

12
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
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@ -205,16 +205,14 @@ bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) {
}
void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) {
MachineBasicBlock &B = *A;
for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
MachineInstr *MI = &*I;
unsigned Opc = MI->getOpcode();
for (MachineBasicBlock &B : MF) {
for (MachineInstr &MI : B) {
unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::C2_tfrpr:
case TargetOpcode::COPY:
if (isPredReg(MI->getOperand(1).getReg())) {
RegisterSubReg RD = MI->getOperand(0);
if (isPredReg(MI.getOperand(1).getReg())) {
RegisterSubReg RD = MI.getOperand(0);
if (RD.R.isVirtual())
PredGPRs.insert(RD);
}

11
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -1014,12 +1014,10 @@ bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
LLVM_DEBUG(dbgs() << "\nhw_loop head, "
<< printMBBReference(**L->block_begin()));
for (MachineBasicBlock *MBB : L->getBlocks()) {
for (MachineBasicBlock::iterator
MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
const MachineInstr *MI = &*MII;
if (isInvalidLoopOperation(MI, IsInnerHWLoop)) {
for (const MachineInstr &MI : *MBB) {
if (isInvalidLoopOperation(&MI, IsInnerHWLoop)) {
LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:";
MI->dump(););
MI.dump(););
return true;
}
}
@ -1960,8 +1958,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
TB = FB = nullptr;
for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
MachineBasicBlock *PB = *I;
for (MachineBasicBlock *PB : Preds) {
if (PB != Latch) {
Tmp2.clear();
bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false);

5
llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
View File

@ -51,9 +51,8 @@ struct Filler : public MachineFunctionPass {
TRI = Subtarget.getRegisterInfo();
bool Changed = false;
for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
++FI)
Changed |= runOnMachineBasicBlock(*FI);
for (MachineBasicBlock &MBB : MF)
Changed |= runOnMachineBasicBlock(MBB);
return Changed;
}

12
llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -637,8 +637,8 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
// has any inline assembly in it. If so, we have to be conservative about
// alignment assumptions, as we don't know for sure the size of any
// instructions in the inline assembly.
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
computeBlockSize(&*I);
for (MachineBasicBlock &MBB : *MF)
computeBlockSize(&MBB);
// Compute block offsets.
adjustBBOffsetsAfter(&MF->front());
@ -1633,10 +1633,10 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
void MipsConstantIslands::prescanForConstants() {
unsigned J = 0;
(void)J;
for (MachineFunction::iterator B =
MF->begin(), E = MF->end(); B != E; ++B) {
for (MachineBasicBlock::instr_iterator I =
B->instr_begin(), EB = B->instr_end(); I != EB; ++I) {
for (MachineBasicBlock &B : *MF) {
for (MachineBasicBlock::instr_iterator I = B.instr_begin(),
EB = B.instr_end();
I != EB; ++I) {
switch(I->getDesc().getOpcode()) {
case Mips::LwConstant32: {
PrescannedForConstants = true;

5
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -218,9 +218,8 @@ namespace {
bool runOnMachineFunction(MachineFunction &F) override {
TM = &F.getTarget();
bool Changed = false;
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI)
Changed |= runOnMachineBasicBlock(*FI);
for (MachineBasicBlock &MBB : F)
Changed |= runOnMachineBasicBlock(MBB);
// This pass invalidates liveness information when it reorders
// instructions to fill delay slot. Without this, -verify-machineinstrs

5
llvm/lib/Target/Mips/MipsExpandPseudo.cpp
View File

@ -896,9 +896,8 @@ bool MipsExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
TII = STI->getInstrInfo();
bool Modified = false;
for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
++MFI)
Modified |= expandMBB(*MFI);
for (MachineBasicBlock &MBB : MF)
Modified |= expandMBB(MBB);
if (Modified)
MF.RenumberBlocks();