forked from OSchip/llvm-project
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description
This commit is contained in:
Dmitry Preobrazhensky
parent
cf396c56e7
commit
5975f1c5f9
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@ -6,7 +6,7 @@
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**************************************************
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====================================================================================
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Syntax of Core GFX10 Instructions
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Syntax of GFX10 RDNA1 Instructions
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====================================================================================
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.. contents::
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@ -15,7 +15,7 @@ Syntax of Core GFX10 Instructions
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Introduction
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============
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This document describes the syntax of *core* GFX10 instructions.
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This document describes the syntax of GFX10 RDNA1 (gfx1010) instructions.
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Notation
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========
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@ -17,7 +17,7 @@ Introduction
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This document describes the syntax of *instructions specific to gfx1011 and gfx1012*.
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For a description of other gfx1011 and gfx1012 instructions see :doc:`Syntax of Core GFX10 Instructions<AMDGPUAsmGFX10>`.
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For a description of other gfx1011 and gfx1012 instructions see :doc:`Syntax of GFX10 RDNA1 Instructions<AMDGPUAsmGFX10>`.
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Notation
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========
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,29 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_attr:
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attr
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====
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Interpolation attribute and channel:
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============== ===================================
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Syntax Description
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============== ===================================
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attr{0..32}.x Attribute 0..32 with *x* channel.
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attr{0..32}.y Attribute 0..32 with *y* channel.
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attr{0..32}.z Attribute 0..32 with *z* channel.
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attr{0..32}.w Attribute 0..32 with *w* channel.
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============== ===================================
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Examples:
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.. parsed-literal::
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v_interp_p1_f32 v1, v0, attr0.x
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v_interp_p1_f32 v1, v0, attr32.w
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@ -0,0 +1,13 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_dst:
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dst
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===
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This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
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@ -0,0 +1,16 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_fx_operand:
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FX Operand
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==========
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This is an *f32* or *f16* operand depending on instruction modifiers:
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* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
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* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
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@ -0,0 +1,82 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_hwreg:
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hwreg
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=====
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Bits of a hardware register being accessed.
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The bits of this operand have the following meaning:
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======= ===================== ============
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Bits Description Value Range
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======= ===================== ============
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5:0 Register *id*. 0..63
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10:6 First bit *offset*. 0..31
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15:11 *Size* in bits. 1..32
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======= ===================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* An *hwreg* value described below.
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==================================== ============================================================================
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Hwreg Value Syntax Description
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==================================== ============================================================================
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hwreg({0..63}) All bits of a register indicated by its *id*.
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hwreg(<*name*>) All bits of a register indicated by its *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
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==================================== ============================================================================
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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==================== ==========================================
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Name Description
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==================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
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HW_REG_HW_ID2 Id of queue, pipeline, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_TBA_LO tba_lo register.
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HW_REG_TBA_HI tba_hi register.
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HW_REG_TMA_LO tma_lo register.
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HW_REG_TMA_HI tma_hi register.
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HW_REG_FLAT_SCR_LO flat_scratch_lo register.
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HW_REG_FLAT_SCR_HI flat_scratch_hi register.
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HW_REG_POPS_PACKER pops_packer register.
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HW_REG_SHADER_CYCLES Current graphics clock counter value.
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==================== ==========================================
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Examples:
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.. parsed-literal::
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reg = 1
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offset = 2
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size = 4
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hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
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s_getreg_b32 s2, 0x1881
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s_getreg_b32 s2, hwreg_enc // the same as above
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s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
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s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
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s_getreg_b32 s2, hwreg(15)
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s_getreg_b32 s2, hwreg(51, 1, 31)
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s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
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@ -0,0 +1,13 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_imm16_73139a:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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@ -0,0 +1,13 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_imm16_a04fb3:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_label:
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label
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=====
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A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
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Examples:
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.. parsed-literal::
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offset = 30
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label_1:
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label_2 = . + 4
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s_branch 32
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s_branch offset + 2
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s_branch label_1
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s_branch label_2
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s_branch label_3
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s_branch label_4
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label_3 = label_2 + 4
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label_4:
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@ -0,0 +1,13 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_m_254bcb:
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m
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=
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This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_m_f5d306:
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m
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=
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This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_msg:
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msg
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===
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A 16-bit message code. The bits of this operand have the following meaning:
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============ =============================== ===============
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Bits Description Value Range
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============ =============================== ===============
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3:0 Message *type*. 0..15
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6:4 Optional *operation*. 0..7
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7:7 Unused. \-
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9:8 Optional *stream*. 0..3
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15:10 Unused. \-
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============ =============================== ===============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* A *sendmsg* value described below.
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==================================== ====================================================
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Sendmsg Value Syntax Description
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==================================== ====================================================
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sendmsg(<*type*>) A message identified by its *type*.
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sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
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sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
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with a stream *id*.
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==================================== ====================================================
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*Type* may be specified using message *name* or message *id*.
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*Op* may be specified using operation *name* or operation *id*.
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Stream *id* is an integer in the range 0..3.
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Each message type supports specific operations:
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====================== ========== ============================== ============ ==========
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Message name Message Id Supported Operations Operation Id Stream Id
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====================== ========== ============================== ============ ==========
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MSG_INTERRUPT 1 \- \- \-
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MSG_GS 2 GS_OP_CUT 1 Optional
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\ GS_OP_EMIT 2 Optional
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\ GS_OP_EMIT_CUT 3 Optional
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MSG_GS_DONE 3 GS_OP_NOP 0 \-
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\ GS_OP_CUT 1 Optional
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\ GS_OP_EMIT 2 Optional
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\ GS_OP_EMIT_CUT 3 Optional
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MSG_SAVEWAVE 4 \- \- \-
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MSG_STALL_WAVE_GEN 5 \- \- \-
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MSG_HALT_WAVES 6 \- \- \-
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MSG_ORDERED_PS_DONE 7 \- \- \-
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MSG_GS_ALLOC_REQ 9 \- \- \-
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MSG_GET_DOORBELL 10 \- \- \-
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MSG_GET_DDID 11 \- \- \-
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MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
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\ SYSMSG_OP_REG_RD 2 \-
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\ SYSMSG_OP_TTRACE_PC 4 \-
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====================== ========== ============================== ============ ==========
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*Sendmsg* arguments are validated depending on how *type* value is specified:
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* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
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* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
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Examples:
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.. parsed-literal::
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// numeric message code
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msg = 0x10
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s_sendmsg 0x12
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s_sendmsg msg + 2
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// sendmsg with strict arguments validation
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s_sendmsg sendmsg(MSG_INTERRUPT)
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s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
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s_sendmsg sendmsg(MSG_GS, 2)
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s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
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s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
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s_sendmsg sendmsg(MSG_GET_DOORBELL)
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// sendmsg with validation of value range only
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msg = 2
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op = 3
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stream = 1
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s_sendmsg sendmsg(msg, op, stream)
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s_sendmsg sendmsg(2, GS_OP_CUT)
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_opt:
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opt
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===
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This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_param:
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param
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=====
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Interpolation parameter to read:
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============ ===================================
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Syntax Description
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============ ===================================
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p0 Parameter *P0*.
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p10 Parameter *P10*.
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p20 Parameter *P20*.
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============ ===================================
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_saddr_9cd3cf:
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saddr
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=====
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A 64-bit flat global address.
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*Size:* 2 dwords.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`off<amdgpu_synid_off>`
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_saddr_beaa25:
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saddr
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=====
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An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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See :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` for description of available addressing modes.
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*Size:* 2 dwords.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_saddr_d75725:
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saddr
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=====
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An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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* Offset = [:ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`] + [:ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>`] + :ref:`offset12s<amdgpu_synid_flat_offset12s>`.
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*Size:* 1 dword.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_sbase_010ce0:
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sbase
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=====
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A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
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*Size:* 4 dwords.
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|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sbase_020892:
|
||||
|
||||
sbase
|
||||
=====
|
||||
|
||||
A 64-bit base address for scalar memory operations.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_0804b1:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_2e4c2a:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_362c37:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 8 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_3759f6:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_386c33:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_3bc700:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 16 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_54e16e:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_8078f5:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_sdst_ea3f10:
|
||||
|
||||
sdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`exec<amdgpu_synid_exec>`
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_simm32_6f0844:
|
||||
|
||||
simm32
|
||||
======
|
||||
|
||||
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
|
||||
The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_simm32_a3e80c:
|
||||
|
||||
simm32
|
||||
======
|
||||
|
||||
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_simm32_be0c1c:
|
||||
|
||||
simm32
|
||||
======
|
||||
|
||||
A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
|
||||
The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_soffset_59fade:
|
||||
|
||||
soffset
|
||||
=======
|
||||
|
||||
An unsigned 20-bit offset added to the base address to get memory address.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_soffset_c40a5a:
|
||||
|
||||
soffset
|
||||
=======
|
||||
|
||||
An offset added to the base address to get memory address.
|
||||
|
||||
* If offset is specified as a register, it supplies an unsigned byte offset.
|
||||
* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_soffset_fef808:
|
||||
|
||||
soffset
|
||||
=======
|
||||
|
||||
An unsigned byte offset.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_37d670:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_516946:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_823582:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_c27036:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_cf1cda:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_d5cd94:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_e0345d:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_src_e9e6db:
|
||||
|
||||
src
|
||||
===
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_srsrc_5dafbc:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
|
||||
Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_srsrc_cf7132:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
|
||||
Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
|
||||
|
||||
*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_srsrc_e73d16:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
|
||||
Buffer resource constant which defines the address and characteristics of the buffer in memory.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssamp:
|
||||
|
||||
ssamp
|
||||
=====
|
||||
|
||||
Sampler constant used to specify filtering options applied to the image data after it is read.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_054e2a:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_2a042f:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_3ec588:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_460c63:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_48e8e7:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_6fbc49:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_7da351:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_81ba27:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_ssrc_9a4448:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_tgt:
|
||||
|
||||
tgt
|
||||
===
|
||||
|
||||
An export target:
|
||||
|
||||
================== ===================================
|
||||
Syntax Description
|
||||
================== ===================================
|
||||
pos{0..4} Copy vertex position 0..4.
|
||||
param{0..31} Copy vertex parameter 0..31.
|
||||
mrt{0..7} Copy pixel color to the MRTs 0..7.
|
||||
mrtz Copy pixel depth (Z) data.
|
||||
prim Copy primitive (connectivity) data.
|
||||
null Copy nothing.
|
||||
================== ===================================
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_type_deviation:
|
||||
|
||||
Type Deviation
|
||||
==============
|
||||
|
||||
*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_373b95:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
|
||||
|
||||
* Offset = [:ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`] + [:ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>`] + :ref:`offset12s<amdgpu_synid_flat_offset12s>`.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_49d53a:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
|
||||
|
||||
This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
|
||||
|
||||
*Size:* 8-12 dwords. Actual size depends on :ref:`a16<amdgpu_synid_a16>`.
|
||||
|
||||
* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
|
||||
* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
|
||||
|
||||
Examples:
|
||||
|
||||
.. parsed-literal::
|
||||
|
||||
image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
|
||||
image_bvh_intersect_ray v[39:42], [v5, v4, v2, v1, v7, v3, v0, v6], s[12:15] a16
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_9aeece:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
|
||||
|
||||
* Address = :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` set to :ref:`off<amdgpu_synid_off>`.
|
||||
* Address = :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` + :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` is not :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 or 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_9f7133:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
A 64-bit flat address.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_b73dc0:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
This is an optional operand which may specify offset and/or index.
|
||||
|
||||
*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
|
||||
|
||||
* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
|
||||
* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
|
||||
* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
|
||||
* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_cdc744:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
|
||||
|
||||
This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
|
||||
|
||||
*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
|
||||
|
||||
* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
|
||||
* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vaddr_f20ee4:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
An offset from the start of GDS/LDS memory.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vcc:
|
||||
|
||||
vcc
|
||||
===
|
||||
|
||||
Vector condition code. This operand depends on wavefront size:
|
||||
|
||||
* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
|
||||
* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata0_6802ce:
|
||||
|
||||
vdata0
|
||||
======
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata0_fd235e:
|
||||
|
||||
vdata0
|
||||
======
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata1_6802ce:
|
||||
|
||||
vdata1
|
||||
======
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata1_fd235e:
|
||||
|
||||
vdata1
|
||||
======
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_15d255:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Image data to store by an *image_store* instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_325b78:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Input data for an atomic instruction.
|
||||
|
||||
Optionally may serve as an output data:
|
||||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
Note: the surface data format is indicated in the image resource constant but not in the instruction.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_4d8ecf:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Input data for an atomic instruction.
|
||||
|
||||
Optionally may serve as an output data:
|
||||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
Note: the surface data format is indicated in the image resource constant but not in the instruction.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_56f215:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 3 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_6802ce:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_87fb90:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Input data for an atomic instruction.
|
||||
|
||||
Optionally may serve as an output data:
|
||||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_b2a787:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Input data for an atomic instruction.
|
||||
|
||||
Optionally may serve as an output data:
|
||||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_c08393:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Image data to store by an *image_store* instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_c61803:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Input data for an atomic instruction.
|
||||
|
||||
Optionally may serve as an output data:
|
||||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_e016a1:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdata_fd235e:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_3d7dcf:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an image instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_463513:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Data returned by a 64-bit atomic flat instruction.
|
||||
|
||||
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_473a69:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an image instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_48d3a8:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an *image_gather4* instruction.
|
||||
|
||||
*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
|
||||
:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
|
||||
|
||||
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_48e42f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 3 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_5d50a1:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_69a144:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_719833:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
|
||||
|
||||
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_89680f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_a49b76:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_bdb32f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_d0dc43:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Data returned by a 32-bit atomic flat instruction.
|
||||
|
||||
This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_d7c57e:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_f47754:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vdst_f8490d:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an image instruction.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vsrc_533a4e:
|
||||
|
||||
vsrc
|
||||
====
|
||||
|
||||
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
|
||||
|
||||
:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
|
||||
|
||||
* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
|
||||
* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
|
||||
|
||||
An example:
|
||||
|
||||
.. parsed-literal::
|
||||
|
||||
exp mrtz v3, v3, off, off compr
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vsrc_6802ce:
|
||||
|
||||
vsrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vsrc_e016a1:
|
||||
|
||||
vsrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx1030_vsrc_fd235e:
|
||||
|
||||
vsrc
|
||||
====
|
||||
|
||||
Instruction input.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
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Loading…
Reference in New Issue