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[NFC][Regalloc] Pass VirtRegMap by reference. 

It's never null - the reason it's modeled as a pointer is because the
pass can't init it in its ctor. Passing by ref simplifies the code, too,
as the null checks were unnecessary complexity.

Differential Revision: https://reviews.llvm.org/D89171
This commit is contained in:
Mircea Trofin 2020-10-09 16:38:42 -07:00
parent c2216d796a
commit 596a9f6b89
6 changed files with 32 additions and 36 deletions
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6
llvm/include/llvm/CodeGen/CalcSpillWeights.h
View File

@ -46,13 +46,13 @@ class VirtRegMap;
class VirtRegAuxInfo {
MachineFunction &MF;
LiveIntervals &LIS;
VirtRegMap *const VRM;
const VirtRegMap &VRM;
const MachineLoopInfo &Loops;
const MachineBlockFrequencyInfo &MBFI;
public:
VirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap *VRM,
const MachineLoopInfo &Loops,
VirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS,
const VirtRegMap &VRM, const MachineLoopInfo &Loops,
const MachineBlockFrequencyInfo &MBFI)
: MF(MF), LIS(LIS), VRM(VRM), Loops(Loops), MBFI(MBFI) {}

52
llvm/lib/CodeGen/CalcSpillWeights.cpp
View File

@ -76,12 +76,11 @@ static Register copyHint(const MachineInstr *MI, unsigned Reg,
}
// Check if all values in LI are rematerializable
static bool isRematerializable(const LiveInterval &LI,
const LiveIntervals &LIS,
VirtRegMap *VRM,
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS,
const VirtRegMap &VRM,
const TargetInstrInfo &TII) {
unsigned Reg = LI.reg();
unsigned Original = VRM ? VRM->getOriginal(Reg) : 0;
unsigned Original = VRM.getOriginal(Reg);
for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
I != E; ++I) {
const VNInfo *VNI = *I;
@ -96,31 +95,28 @@ static bool isRematerializable(const LiveInterval &LI,
// Trace copies introduced by live range splitting. The inline
// spiller can rematerialize through these copies, so the spill
// weight must reflect this.
if (VRM) {
while (MI->isFullCopy()) {
// The copy destination must match the interval register.
if (MI->getOperand(0).getReg() != Reg)
return false;
while (MI->isFullCopy()) {
// The copy destination must match the interval register.
if (MI->getOperand(0).getReg() != Reg)
return false;
// Get the source register.
Reg = MI->getOperand(1).getReg();
// Get the source register.
Reg = MI->getOperand(1).getReg();
// If the original (pre-splitting) registers match this
// copy came from a split.
if (!Register::isVirtualRegister(Reg) ||
VRM->getOriginal(Reg) != Original)
return false;
// If the original (pre-splitting) registers match this
// copy came from a split.
if (!Register::isVirtualRegister(Reg) || VRM.getOriginal(Reg) != Original)
return false;
// Follow the copy live-in value.
const LiveInterval &SrcLI = LIS.getInterval(Reg);
LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
VNI = SrcQ.valueIn();
assert(VNI && "Copy from non-existing value");
if (VNI->isPHIDef())
return false;
MI = LIS.getInstructionFromIndex(VNI->def);
assert(MI && "Dead valno in interval");
}
// Follow the copy live-in value.
const LiveInterval &SrcLI = LIS.getInterval(Reg);
LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
VNI = SrcQ.valueIn();
assert(VNI && "Copy from non-existing value");
if (VNI->isPHIDef())
return false;
MI = LIS.getInstructionFromIndex(VNI->def);
assert(MI && "Dead valno in interval");
}
if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis()))
@ -155,9 +151,9 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
std::pair<Register, Register> TargetHint = MRI.getRegAllocationHint(LI.reg());
if (LI.isSpillable() && VRM) {
if (LI.isSpillable()) {
Register Reg = LI.reg();
Register Original = VRM->getOriginal(Reg);
Register Original = VRM.getOriginal(Reg);
const LiveInterval &OrigInt = LIS.getInterval(Original);
// li comes from a split of OrigInt. If OrigInt was marked
// as not spillable, make sure the new interval is marked

2
llvm/lib/CodeGen/LiveRangeEdit.cpp
View File

@ -463,7 +463,7 @@ void
LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
const MachineLoopInfo &Loops,
const MachineBlockFrequencyInfo &MBFI) {
VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
VirtRegAuxInfo VRAI(MF, LIS, *VRM, Loops, MBFI);
for (unsigned I = 0, Size = size(); I < Size; ++I) {
LiveInterval &LI = LIS.getInterval(get(I));
if (MRI.recomputeRegClass(LI.reg()))

2
llvm/lib/CodeGen/RegAllocBasic.cpp
View File

@ -312,7 +312,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
RegAllocBase::init(getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervals>(),
getAnalysis<LiveRegMatrix>());
VirtRegAuxInfo VRAI(*MF, *LIS, VRM, getAnalysis<MachineLoopInfo>(),
VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, getAnalysis<MachineLoopInfo>(),
getAnalysis<MachineBlockFrequencyInfo>());
VRAI.calculateSpillWeightsAndHints();

2
llvm/lib/CodeGen/RegAllocGreedy.cpp
View File

@ -3234,7 +3234,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
initializeCSRCost();
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, VRM, *Loops, *MBFI);
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
VRAI->calculateSpillWeightsAndHints();

4
llvm/lib/CodeGen/RegAllocPBQP.cpp
View File

@ -527,7 +527,7 @@ class PBQPVirtRegAuxInfo final : public VirtRegAuxInfo {
}
public:
PBQPVirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap *VRM,
PBQPVirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
const MachineLoopInfo &Loops,
const MachineBlockFrequencyInfo &MBFI)
: VirtRegAuxInfo(MF, LIS, VRM, Loops, MBFI) {}
@ -799,7 +799,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
VirtRegMap &VRM = getAnalysis<VirtRegMap>();
PBQPVirtRegAuxInfo VRAI(MF, LIS, &VRM, getAnalysis<MachineLoopInfo>(), MBFI);
PBQPVirtRegAuxInfo VRAI(MF, LIS, VRM, getAnalysis<MachineLoopInfo>(), MBFI);
VRAI.calculateSpillWeightsAndHints();
std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));