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[X86][NFC] Use mnemonic tables in validateInstruction 4/4 

Group switch cases by opcode:
- VGATHERDPD
- VGATHERDPS
- VGATHERQPD
- VGATHERQPS
- VPGATHERDD
- VPGATHERDQ
- VPGATHERQD
- VPGATHERQQ

Distinguish masked vs non-masked forms by EVEX encoding.

Reviewed By: skan, craig.topper

Differential Revision: https://reviews.llvm.org/D127719
This commit is contained in:
Amir Ayupov 2022-06-14 19:53:28 -07:00 committed by Amir Aupov
parent 701a282af4
commit 5965878d4d
1 changed files with 24 additions and 63 deletions
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87
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -3836,6 +3836,7 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
using namespace X86;
const MCRegisterInfo *MRI = getContext().getRegisterInfo();
unsigned Opcode = Inst.getOpcode();
uint64_t TSFlags = MII.get(Opcode).TSFlags;
if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) ||
isVFMADDCSH(Opcode)) {
unsigned Dest = Inst.getOperand(0).getReg();
@ -3866,74 +3867,34 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
RegName.take_front(3) + Twine(GroupEnd) +
"' source group");
}
} else if (isVGATHERDPD(Opcode) || isVGATHERDPS(Opcode) ||
isVGATHERQPD(Opcode) || isVGATHERQPS(Opcode) ||
isVPGATHERDD(Opcode) || isVPGATHERDQ(Opcode) ||
isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) {
bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
if (HasEVEX) {
unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Index = MRI->getEncodingValue(
Inst.getOperand(4 + X86::AddrIndexReg).getReg());
if (Dest == Index)
return Warning(Ops[0]->getStartLoc(), "index and destination registers "
"should be distinct");
} else {
unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
unsigned Index = MRI->getEncodingValue(
Inst.getOperand(3 + X86::AddrIndexReg).getReg());
if (Dest == Mask || Dest == Index || Mask == Index)
return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
"registers should be distinct");
}
}
switch (Inst.getOpcode()) {
case X86::VGATHERDPDYrm:
case X86::VGATHERDPDrm:
case X86::VGATHERDPSYrm:
case X86::VGATHERDPSrm:
case X86::VGATHERQPDYrm:
case X86::VGATHERQPDrm:
case X86::VGATHERQPSYrm:
case X86::VGATHERQPSrm:
case X86::VPGATHERDDYrm:
case X86::VPGATHERDDrm:
case X86::VPGATHERDQYrm:
case X86::VPGATHERDQrm:
case X86::VPGATHERQDYrm:
case X86::VPGATHERQDrm:
case X86::VPGATHERQQYrm:
case X86::VPGATHERQQrm: {
unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
unsigned Index =
MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg());
if (Dest == Mask || Dest == Index || Mask == Index)
return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
"registers should be distinct");
break;
}
case X86::VGATHERDPDZ128rm:
case X86::VGATHERDPDZ256rm:
case X86::VGATHERDPDZrm:
case X86::VGATHERDPSZ128rm:
case X86::VGATHERDPSZ256rm:
case X86::VGATHERDPSZrm:
case X86::VGATHERQPDZ128rm:
case X86::VGATHERQPDZ256rm:
case X86::VGATHERQPDZrm:
case X86::VGATHERQPSZ128rm:
case X86::VGATHERQPSZ256rm:
case X86::VGATHERQPSZrm:
case X86::VPGATHERDDZ128rm:
case X86::VPGATHERDDZ256rm:
case X86::VPGATHERDDZrm:
case X86::VPGATHERDQZ128rm:
case X86::VPGATHERDQZ256rm:
case X86::VPGATHERDQZrm:
case X86::VPGATHERQDZ128rm:
case X86::VPGATHERQDZ256rm:
case X86::VPGATHERQDZrm:
case X86::VPGATHERQQZ128rm:
case X86::VPGATHERQQZ256rm:
case X86::VPGATHERQQZrm: {
unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Index =
MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg());
if (Dest == Index)
return Warning(Ops[0]->getStartLoc(), "index and destination registers "
"should be distinct");
break;
}
}
const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
// Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to
// check this with the legacy encoding, VEX/EVEX/XOP don't use REX.
if ((MCID.TSFlags & X86II::EncodingMask) == 0) {
if ((TSFlags & X86II::EncodingMask) == 0) {
MCPhysReg HReg = X86::NoRegister;
bool UsesRex = MCID.TSFlags & X86II::REX_W;
bool UsesRex = TSFlags & X86II::REX_W;
unsigned NumOps = Inst.getNumOperands();
for (unsigned i = 0; i != NumOps; ++i) {
const MCOperand &MO = Inst.getOperand(i);