From 594a3ba40ed3f49478d4dea484913187512d8e1d Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Wed, 27 Jul 2005 23:11:27 +0000 Subject: [PATCH] Fix some comments llvm-svn: 22530 --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 4 +--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index ee794911d604..a21cf5b83eea 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -1656,9 +1656,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; case ISD::AND: - // FIXME: should add check in getImmediateForOpcode to return a value - // indicating the immediate is a run of set bits so we can emit a bitfield - // clear with RLWINM instead. switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) { default: assert(0 && "unhandled result code"); case 0: // No immediate @@ -1690,6 +1687,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { Tmp3 = Tmp2 >> 16; // MB Tmp2 &= 0xFFFF; // ME + // FIXME: Catch SHL-AND in addition to SRL-AND in this block. if (N.getOperand(0).getOpcode() == ISD::SRL) if (ConstantSDNode *SA = dyn_cast(N.getOperand(0).getOperand(1))) { diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp index 7977a0050010..3493fdc02a1c 100644 --- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp @@ -263,7 +263,7 @@ void PPC32RegisterInfo::emitPrologue(MachineFunction &MF) const { // Update frame info to pretend that this is part of the stack... MFI->setStackSize(NumBytes); - // If , adjust stack pointer: r1 -= numbytes. + // Adjust stack pointer: r1 -= numbytes. if (NumBytes <= 32768) { MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); MBB.insert(MBBI, MI);