forked from OSchip/llvm-project
Second half of my fixed-sized-alloca patch. This folds the LEA to compute
the alloca address into common operations like loads/stores.
In a simple testcase like this (which is just designed to excersize the
alloca A, nothing more):
int %test(int %X, bool %C) {
%A = alloca int
store int %X, int* %A
store int* %A, int** %G
br bool %C, label %T, label %F
T:
call int %test(int 1, bool false)
%V = load int* %A
ret int %V
F:
call int %test(int 123, bool true)
%V2 = load int* %A
ret int %V2
}
We now generate:
test:
sub %ESP, 12
mov %EAX, DWORD PTR [%ESP + 16]
mov %CL, BYTE PTR [%ESP + 20]
*** mov DWORD PTR [%ESP + 8], %EAX
mov %EAX, OFFSET G
lea %EDX, DWORD PTR [%ESP + 8]
mov DWORD PTR [%EAX], %EDX
test %CL, %CL
je .LBB2 # PC rel: F
.LBB1: # T
mov DWORD PTR [%ESP], 1
mov DWORD PTR [%ESP + 4], 0
call test
*** mov %EAX, DWORD PTR [%ESP + 8]
add %ESP, 12
ret
.LBB2: # F
mov DWORD PTR [%ESP], 123
mov DWORD PTR [%ESP + 4], 1
call test
*** mov %EAX, DWORD PTR [%ESP + 8]
add %ESP, 12
ret
Instead of:
test:
sub %ESP, 20
mov %EAX, DWORD PTR [%ESP + 24]
mov %CL, BYTE PTR [%ESP + 28]
*** lea %EDX, DWORD PTR [%ESP + 16]
*** mov DWORD PTR [%EDX], %EAX
mov %EAX, OFFSET G
mov DWORD PTR [%EAX], %EDX
test %CL, %CL
*** mov DWORD PTR [%ESP + 12], %EDX
je .LBB2 # PC rel: F
.LBB1: # T
mov DWORD PTR [%ESP], 1
mov %EAX, 0
mov DWORD PTR [%ESP + 4], %EAX
call test
*** mov %EAX, DWORD PTR [%ESP + 12]
*** mov %EAX, DWORD PTR [%EAX]
add %ESP, 20
ret
.LBB2: # F
mov DWORD PTR [%ESP], 123
mov %EAX, 1
mov DWORD PTR [%ESP + 4], %EAX
call test
*** mov %EAX, DWORD PTR [%ESP + 12]
*** mov %EAX, DWORD PTR [%EAX]
add %ESP, 20
ret
llvm-svn: 13557
This commit is contained in:
Chris Lattner
parent
2bb3325965
commit
593d22d666
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@ -814,6 +814,25 @@ void ISel::InsertFPRegKills() {
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}
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void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
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unsigned &IndexReg, unsigned &Disp) {
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BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
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if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
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if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
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BaseReg, Scale, IndexReg, Disp))
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return;
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
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if (CE->getOpcode() == Instruction::GetElementPtr)
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if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
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BaseReg, Scale, IndexReg, Disp))
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return;
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}
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// If it's not foldable, reset addr mode.
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BaseReg = getReg(Addr);
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Scale = 1; IndexReg = 0; Disp = 0;
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}
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// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
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// it into the conditional branch or select instruction which is the only user
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// of the cc instruction. This is the case if the conditional branch is the
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@ -1953,13 +1972,20 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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Opcode = OpcodeTab[OperatorClass][Ty == Type::DoubleTy];
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}
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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unsigned Op0r = getReg(Op0);
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addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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if (AllocaInst *AI =
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dyn_castFixedAlloca(cast<LoadInst>(Op1)->getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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}
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return;
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}
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@ -1972,13 +1998,19 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned Opcode = Ty == Type::FloatTy ? X86::FSUBR32m : X86::FSUBR64m;
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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unsigned Op1r = getReg(Op1);
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addFullAddress(BuildMI(BB, Opcode, 2, DestReg).addReg(Op1r),
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BaseReg, Scale, IndexReg, Disp);
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if (AllocaInst *AI =
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dyn_castFixedAlloca(cast<LoadInst>(Op0)->getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r),
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BaseReg, Scale, IndexReg, Disp);
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}
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return;
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}
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@ -2337,13 +2369,18 @@ void ISel::visitMul(BinaryOperator &I) {
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assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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unsigned Op0r = getReg(Op0);
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addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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}
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return;
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}
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}
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@ -2476,13 +2513,18 @@ void ISel::visitDivRem(BinaryOperator &I) {
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assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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unsigned Op0r = getReg(Op0);
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addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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}
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return;
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}
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@ -2492,13 +2534,16 @@ void ISel::visitDivRem(BinaryOperator &I) {
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assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
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unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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unsigned Op1r = getReg(Op1);
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addFullAddress(BuildMI(BB, Opcode, 2, ResultReg).addReg(Op1r),
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BaseReg, Scale, IndexReg, Disp);
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if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r),
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BaseReg, Scale, IndexReg, Disp);
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}
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return;
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}
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}
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@ -2796,26 +2841,6 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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}
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void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
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unsigned &IndexReg, unsigned &Disp) {
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BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
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if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
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if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
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BaseReg, Scale, IndexReg, Disp))
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return;
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
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if (CE->getOpcode() == Instruction::GetElementPtr)
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if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
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BaseReg, Scale, IndexReg, Disp))
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return;
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}
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// If it's not foldable, reset addr mode.
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BaseReg = getReg(Addr);
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Scale = 1; IndexReg = 0; Disp = 0;
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}
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// instruction. The load and store instructions are the only place where we
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/// need to worry about the memory layout of the target machine.
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@ -2838,10 +2863,16 @@ void ISel::visitLoadInst(LoadInst &I) {
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static const unsigned Opcode[] = {
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0/*BYTE*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m
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};
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unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
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getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode[Class], 5, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode[Class], 4, DestReg), FI);
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} else {
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unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
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getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode[Class], 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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}
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return;
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} else {
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User = 0;
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@ -2887,33 +2918,49 @@ void ISel::visitLoadInst(LoadInst &I) {
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}
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}
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unsigned DestReg = getReg(I);
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unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
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getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
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if (Class == cLong) {
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
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BaseReg, Scale, IndexReg, Disp+4);
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return;
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}
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static const unsigned Opcodes[] = {
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X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m
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X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m, X86::MOV32rm
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};
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unsigned Opcode = Opcodes[Class];
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if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
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addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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unsigned DestReg = getReg(I);
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if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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if (Class == cLong) {
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addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg), FI);
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addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), FI, 4);
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} else {
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addFrameReference(BuildMI(BB, Opcode, 4, DestReg), FI);
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}
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} else {
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unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
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getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
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if (Class == cLong) {
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
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BaseReg, Scale, IndexReg, Disp+4);
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} else {
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addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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}
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}
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}
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/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
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/// instruction.
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///
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void ISel::visitStoreInst(StoreInst &I) {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
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unsigned BaseReg = ~0U, Scale = ~0U, IndexReg = ~0U, Disp = ~0U;
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unsigned AllocaFrameIdx = ~0U;
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if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(1)))
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AllocaFrameIdx = getFixedSizedAllocaFI(AI);
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else
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getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
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const Type *ValTy = I.getOperand(0)->getType();
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unsigned Class = getClassB(ValTy);
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@ -2921,21 +2968,36 @@ void ISel::visitStoreInst(StoreInst &I) {
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
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uint64_t Val = CI->getRawValue();
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if (Class == cLong) {
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
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if (AllocaFrameIdx != ~0U) {
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx).addImm(Val & ~0U);
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx, 4).addImm(Val>>32);
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} else {
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
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}
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} else {
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static const unsigned Opcodes[] = {
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X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
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};
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unsigned Opcode = Opcodes[Class];
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addFullAddress(BuildMI(BB, Opcode, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(Val);
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if (AllocaFrameIdx != ~0U) {
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addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addImm(Val);
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} else {
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addFullAddress(BuildMI(BB, Opcode, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(Val);
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}
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}
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} else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
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addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
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AllocaFrameIdx).addImm(CB->getValue());
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else
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addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
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} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) {
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// Store constant FP values with integer instructions to avoid having to
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// load the constants from the constant pool then do a store.
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@ -2945,27 +3007,45 @@ void ISel::visitStoreInst(StoreInst &I) {
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float F;
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} V;
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V.F = CFP->getValue();
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(V.I);
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx).addImm(V.I);
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else
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(V.I);
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} else {
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union {
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uint64_t I;
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double F;
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} V;
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V.F = CFP->getValue();
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm((unsigned)V.I);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp+4).addImm(
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if (AllocaFrameIdx != ~0U) {
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
|
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AllocaFrameIdx).addImm((unsigned)V.I);
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx, 4).addImm(unsigned(V.I >> 32));
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} else {
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
|
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BaseReg, Scale, IndexReg, Disp).addImm((unsigned)V.I);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp+4).addImm(
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unsigned(V.I >> 32));
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}
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}
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||||
|
||||
} else if (Class == cLong) {
|
||||
unsigned ValReg = getReg(I.getOperand(0));
|
||||
addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
|
||||
BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
|
||||
addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
|
||||
BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
|
||||
if (AllocaFrameIdx != ~0U) {
|
||||
addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
|
||||
AllocaFrameIdx).addReg(ValReg);
|
||||
addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
|
||||
AllocaFrameIdx, 4).addReg(ValReg+1);
|
||||
} else {
|
||||
addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
|
||||
BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
|
||||
addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
|
||||
BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
|
||||
}
|
||||
} else {
|
||||
unsigned ValReg = getReg(I.getOperand(0));
|
||||
static const unsigned Opcodes[] = {
|
||||
|
|
@ -2973,8 +3053,12 @@ void ISel::visitStoreInst(StoreInst &I) {
|
|||
};
|
||||
unsigned Opcode = Opcodes[Class];
|
||||
if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
|
||||
addFullAddress(BuildMI(BB, Opcode, 1+4),
|
||||
BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
|
||||
|
||||
if (AllocaFrameIdx != ~0U)
|
||||
addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addReg(ValReg);
|
||||
else
|
||||
addFullAddress(BuildMI(BB, Opcode, 1+4),
|
||||
BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3627,13 +3711,15 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/// visitAllocaInst - If this is a fixed size alloca, allocate space from the
|
||||
/// frame manager, otherwise do it the hard way.
|
||||
///
|
||||
void ISel::visitAllocaInst(AllocaInst &I) {
|
||||
// If this is a fixed size alloca in the entry block for the function, we
|
||||
// statically stack allocate the space, so we don't need to do anything here.
|
||||
//
|
||||
if (dyn_castFixedAlloca(&I)) return;
|
||||
|
||||
|
||||
// Find the data size of the alloca inst's getAllocatedType.
|
||||
const Type *Ty = I.getAllocatedType();
|
||||
unsigned TySize = TM.getTargetData().getTypeSize(Ty);
|
||||
|
|
|
|||
Loading…
Reference in New Issue