maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions 

See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839

Differential Revision: https://reviews.llvm.org/D45249

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329408
This commit is contained in:
Dmitry Preobrazhensky 2018-04-06 15:48:39 +00:00
parent d55ad63bfe
commit 59399ae4cc
3 changed files with 56 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
llvm/lib/Target/AMDGPU/SMInstructions.td
View File

@ -63,6 +63,18 @@ class SM_Real <SM_Pseudo ps>
bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
}
class SM_Probe_Pseudo <string opName, dag ins, bit isImm>
: SM_Pseudo<opName, (outs), ins, " $sdata, $sbase, $offset"> {
let mayLoad = 0;
let mayStore = 0;
let has_glc = 0;
let LGKM_CNT = 0;
let ScalarStore = 0;
let hasSideEffects = 1;
let offset_is_imm = isImm;
let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
}
class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
: SM_Pseudo<opName, outs, ins, asmOps, pattern> {
RegisterClass BaseClass;
@ -161,6 +173,11 @@ class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
let has_offset = 0;
}
multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> {
def _IMM : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, smrd_offset_20:$offset), 1>;
def _SGPR : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, SReg_32:$offset), 0>;
}
//===----------------------------------------------------------------------===//
// Scalar Atomic Memory Classes
//===----------------------------------------------------------------------===//
@ -277,6 +294,9 @@ let SubtargetPredicate = isVI in {
def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
defm S_ATC_PROBE : SM_Pseudo_Probe <"s_atc_probe", SReg_64>;
defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <"s_atc_probe_buffer", SReg_128>;
} // SubtargetPredicate = isVI
let SubtargetPredicate = HasFlatScratchInsts, Uses = [FLAT_SCR] in {
@ -544,6 +564,11 @@ multiclass SM_Real_Stores_vi<bits<8> op, string ps,
}
}
multiclass SM_Real_Probe_vi<bits<8> op, string ps> {
def _IMM_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
def _SGPR_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
}
defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
@ -579,6 +604,9 @@ defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_vi <0x15, "S_SCRATCH_STORE_DWORD">
defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_vi <0x16, "S_SCRATCH_STORE_DWORDX2">;
defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_vi <0x17, "S_SCRATCH_STORE_DWORDX4">;
defm S_ATC_PROBE : SM_Real_Probe_vi <0x26, "S_ATC_PROBE">;
defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27, "S_ATC_PROBE_BUFFER">;
//===----------------------------------------------------------------------===//
// GFX9
//===----------------------------------------------------------------------===//

16
llvm/test/MC/AMDGPU/smem.s
View File

@ -16,6 +16,22 @@ s_dcache_wb_vol
// GFX89: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
s_atc_probe 0x7, s[4:5], s0
// GFX89: s_atc_probe 7, s[4:5], s0 ; encoding: [0xc2,0x01,0x98,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
s_atc_probe 0x0, s[4:5], 0x0
// GFX89: s_atc_probe 0, s[4:5], 0x0 ; encoding: [0x02,0x00,0x9a,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
s_atc_probe_buffer 0x1, s[8:11], s0
// GFX89: s_atc_probe_buffer 1, s[8:11], s0 ; encoding: [0x44,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
s_atc_probe_buffer 0x0, s[8:11], s101
// GFX89: s_atc_probe_buffer 0, s[8:11], s101 ; encoding: [0x04,0x00,0x9c,0xc0,0x65,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU
s_memrealtime s[4:5]
// GFX89: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
// NOSICI: error: instruction not supported on this GPU

12
llvm/test/MC/Disassembler/AMDGPU/smem_vi.txt
View File

@ -44,3 +44,15 @@
# VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
0x2e 0x02 0x29 0xc0 0x7c 0x00 0x00 0x00
# VI: s_atc_probe 7, s[4:5], s0 ; encoding: [0xc2,0x01,0x98,0xc0,0x00,0x00,0x00,0x00]
0xc2,0x01,0x98,0xc0,0x00,0x00,0x00,0x00
# VI: s_atc_probe 0, s[4:5], 0x0 ; encoding: [0x02,0x00,0x9a,0xc0,0x00,0x00,0x00,0x00]
0x02,0x00,0x9a,0xc0,0x00,0x00,0x00,0x00
# VI: s_atc_probe_buffer 1, s[8:11], s0 ; encoding: [0x44,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
0x44,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00
# VI: s_atc_probe_buffer 0, s[8:11], s101 ; encoding: [0x04,0x00,0x9c,0xc0,0x65,0x00,0x00,0x00]
0x04,0x00,0x9c,0xc0,0x65,0x00,0x00,0x00