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AMDGPU: Make various NamedOperands upper case 

Summary:
Avoid name clashes with the corresponding bit fields in the instruction
encoding.

Change-Id: Id1644e703e976e78f7af93788d9f44cb48c3251f

Reviewers: arsenm, rampitec, kzhuravl

Subscribers: wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D47433

llvm-svn: 333905
This commit is contained in:
Nicolai Haehnle 2018-06-04 14:45:20 +00:00
parent ab390f0c41
commit 59198ed040
4 changed files with 43 additions and 43 deletions
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28
llvm/lib/Target/AMDGPU/BUFInstructions.td
View File

@ -142,17 +142,17 @@ class getMTBUFInsDA<list<RegisterClass> vdataList,
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
dag InsNoData = !if(!empty(vaddrList),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, slc:$slc, tfe:$tfe),
offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, SLC:$slc, TFE:$tfe),
(ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, slc:$slc, tfe:$tfe)
offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc, SLC:$slc, TFE:$tfe)
);
dag InsData = !if(!empty(vaddrList),
(ins vdataClass:$vdata, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc,
slc:$slc, tfe:$tfe),
SLC:$slc, TFE:$tfe),
(ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc,
slc:$slc, tfe:$tfe)
SLC:$slc, TFE:$tfe)
);
dag ret = !if(!empty(vdataList), InsNoData, InsData);
}
@ -382,19 +382,19 @@ class getMUBUFInsDA<list<RegisterClass> vdataList,
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
dag InsNoData = !if(!empty(vaddrList),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, GLC:$glc, slc:$slc),
offset:$offset, GLC:$glc, SLC:$slc),
(ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
offset:$offset, GLC:$glc, slc:$slc)
offset:$offset, GLC:$glc, SLC:$slc)
);
dag InsData = !if(!empty(vaddrList),
(ins vdataClass:$vdata, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc),
SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc),
(ins vdataClass:$vdata, vaddrClass:$vaddr, SReg_128:$srsrc,
SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc)
SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc)
);
dag ret = !con(
!if(!empty(vdataList), InsNoData, InsData),
!if(isLds, (ins), (ins tfe:$tfe))
!if(isLds, (ins), (ins TFE:$tfe))
);
}
@ -552,7 +552,7 @@ multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
class MUBUF_Pseudo_Store_Lds<string opName>
: MUBUF_Pseudo<opName,
(outs),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc),
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, GLC:$glc, SLC:$slc),
" $srsrc, $soffset$offset lds$glc$slc"> {
let mayLoad = 0;
let mayStore = 1;
@ -573,15 +573,15 @@ class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in,
dag ret = !if(vdata_in,
!if(!empty(vaddrList),
(ins vdataClass:$vdata_in,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc),
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc),
(ins vdataClass:$vdata_in, vaddrClass:$vaddr,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc)
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc)
),
!if(!empty(vaddrList),
(ins vdataClass:$vdata,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc),
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc),
(ins vdataClass:$vdata, vaddrClass:$vaddr,
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, slc:$slc)
SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, SLC:$slc)
));
}

24
llvm/lib/Target/AMDGPU/FLATInstructions.td
View File

@ -135,7 +135,7 @@ class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
!con((ins VReg_64:$vaddr),
!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
(ins GLC:$glc, slc:$slc)),
(ins GLC:$glc, SLC:$slc)),
!if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
" $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
let has_data = 0;
@ -158,7 +158,7 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
!con((ins VReg_64:$vaddr, vdataClass:$vdata),
!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
(ins GLC:$glc, slc:$slc)),
(ins GLC:$glc, SLC:$slc)),
" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
let mayLoad = 0;
let mayStore = 1;
@ -188,8 +188,8 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
opName,
(outs regClass:$vdst),
!if(EnableSaddr,
(ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc),
(ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc)),
(ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc),
(ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc)),
" $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc"> {
let has_data = 0;
let mayLoad = 1;
@ -204,8 +204,8 @@ class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit En
opName,
(outs),
!if(EnableSaddr,
(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc),
(ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc)),
(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc),
(ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc)),
" "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc"> {
let mayLoad = 0;
let mayStore = 1;
@ -260,7 +260,7 @@ multiclass FLAT_Atomic_Pseudo<
RegisterClass data_rc = vdst_rc> {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
" $vaddr, $vdata$offset$slc">,
AtomicNoRet <opName, 0> {
let PseudoInstr = NAME;
@ -268,7 +268,7 @@ multiclass FLAT_Atomic_Pseudo<
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
" $vdst, $vaddr, $vdata$offset glc$slc",
[(set vt:$vdst,
(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
@ -285,7 +285,7 @@ multiclass FLAT_Global_Atomic_Pseudo<
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, SLC:$slc),
" $vaddr, $vdata, off$offset$slc">,
AtomicNoRet <opName, 0> {
let has_saddr = 1;
@ -294,7 +294,7 @@ multiclass FLAT_Global_Atomic_Pseudo<
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, SLC:$slc),
" $vdst, $vaddr, $vdata, off$offset glc$slc",
[(set vt:$vdst,
(atomic (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
@ -304,7 +304,7 @@ multiclass FLAT_Global_Atomic_Pseudo<
def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, SLC:$slc),
" $vaddr, $vdata, $saddr$offset$slc">,
AtomicNoRet <opName#"_saddr", 0> {
let has_saddr = 1;
@ -314,7 +314,7 @@ multiclass FLAT_Global_Atomic_Pseudo<
def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, SLC:$slc),
" $vdst, $vaddr, $vdata, $saddr$offset glc$slc">,
AtomicNoRet <opName#"_saddr", 1> {
let has_saddr = 1;

20
llvm/lib/Target/AMDGPU/MIMGInstructions.td
View File

@ -41,8 +41,8 @@ class MIMG_NoSampler_Helper <bits<7> op, string asm,
string dns=""> : MIMG_Helper <
(outs dst_rc:$vdata),
(ins addr_rc:$vaddr, SReg_256:$srsrc,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""),
dns>, MIMGe<op> {
let ssamp = 0;
@ -101,8 +101,8 @@ class MIMG_Store_Helper <bits<7> op, string asm,
string dns = ""> : MIMG_Helper <
(outs),
(ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""), dns>, MIMGe<op> {
let ssamp = 0;
let mayLoad = 0;
@ -163,8 +163,8 @@ class MIMG_Atomic_Helper <string asm, RegisterClass data_rc,
bit enableDasm = 0> : MIMG_Helper <
(outs data_rc:$vdst),
(ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da",
!if(enableDasm, dns, "")> {
let mayLoad = 1;
@ -250,8 +250,8 @@ class MIMG_Sampler_Helper <bits<7> op, string asm,
string dns=""> : MIMG_Helper <
(outs dst_rc:$vdata),
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""),
dns>, MIMGe<op> {
let WQM = wqm;
@ -310,8 +310,8 @@ class MIMG_Gather_Helper <bits<7> op, string asm,
string dns=""> : MIMG <
(outs dst_rc:$vdata),
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
R128:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""),
[]>, MIMGe<op> {
let mayLoad = 1;

14
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -848,20 +848,20 @@ def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
def SLC : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
def UNorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
def DA : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
def R128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>;
def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
def DFMT : NamedOperandU8<"DFMT", NamedMatchClass<"DFMT">>;
def NFMT : NamedOperandU8<"NFMT", NamedMatchClass<"NFMT">>;
def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
def DMask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;