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implement CodeGen/X86/inline-asm-x-scalar.ll 

llvm-svn: 35799
This commit is contained in:
Chris Lattner 2007-04-09 05:11:28 +00:00
parent 8a06ca02d8
commit 590ed5e5b7
1 changed files with 15 additions and 1 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -4640,7 +4640,6 @@ isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG); return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
} }
std::vector<unsigned> X86TargetLowering:: std::vector<unsigned> X86TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint, getRegClassForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const { MVT::ValueType VT) const {
@ -4709,6 +4708,21 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
std::pair<unsigned, const TargetRegisterClass*> std::pair<unsigned, const TargetRegisterClass*>
X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const { MVT::ValueType VT) const {
// First, see if this is a constraint that directly corresponds to an LLVM
// register class.
if (Constraint.size() == 1) {
// GCC Constraint Letters
switch (Constraint[0]) {
default: break;
case 'x':
if (VT == MVT::f32)
return std::make_pair(0U, X86::FR32RegisterClass);
if (VT == MVT::f64)
return std::make_pair(0U, X86::FR64RegisterClass);
break;
}
}
// Use the default implementation in TargetLowering to convert the register // Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class. // constraint into a member of a register class.
std::pair<unsigned, const TargetRegisterClass*> Res; std::pair<unsigned, const TargetRegisterClass*> Res;