From 590ed5e5b7d9d7ac2179093c93231b55bb47e8e5 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 9 Apr 2007 05:11:28 +0000
Subject: [PATCH] implement CodeGen/X86/inline-asm-x-scalar.ll

llvm-svn: 35799
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4c54a285cd38..94305eef5b74 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4640,7 +4640,6 @@ isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
   return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
 }
 
-
 std::vector<unsigned> X86TargetLowering::
 getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                   MVT::ValueType VT) const {
@@ -4709,6 +4708,21 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
 std::pair<unsigned, const TargetRegisterClass*>
 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 MVT::ValueType VT) const {
+  // First, see if this is a constraint that directly corresponds to an LLVM
+  // register class.
+  if (Constraint.size() == 1) {
+    // GCC Constraint Letters
+    switch (Constraint[0]) {
+    default: break;
+    case 'x': 
+      if (VT == MVT::f32)
+        return std::make_pair(0U, X86::FR32RegisterClass);
+      if (VT == MVT::f64)
+        return std::make_pair(0U, X86::FR64RegisterClass);
+      break;
+    }
+  }
+  
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.
   std::pair<unsigned, const TargetRegisterClass*> Res;