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[AMDGPU] Run SIShrinkInstructions before post-RA scheduling 

Run post-RA SIShrinkInstructions just before post-RA scheduling, instead
of afterwards. After the fixes in D112305 and D112317 this seems to make
no difference, but it paves the way for scheduler tweaks that are
sensitive to the e32 vs e64 encoding of VALU instructions.

Differential Revision: https://reviews.llvm.org/D112341
This commit is contained in:
Jay Foad 2021-10-22 11:19:29 +01:00
parent 42e4959253
commit 58e7ec471c
2 changed files with 6 additions and 7 deletions
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5
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -1327,6 +1327,8 @@ void GCNPassConfig::addPostRegAlloc() {
}
void GCNPassConfig::addPreSched2() {
if (TM->getOptLevel() > CodeGenOpt::None)
addPass(createSIShrinkInstructionsPass());
addPass(&SIPostRABundlerID);
}
@ -1334,9 +1336,6 @@ void GCNPassConfig::addPreEmitPass() {
addPass(createSIMemoryLegalizerPass());
addPass(createSIInsertWaitcntsPass());
if (TM->getOptLevel() > CodeGenOpt::None)
addPass(createSIShrinkInstructionsPass());
addPass(createSIModeRegisterPass());
if (getOptLevel() > CodeGenOpt::None)

8
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
View File

@ -367,6 +367,7 @@
; GCN-O1-NEXT: Tail Duplication
; GCN-O1-NEXT: Machine Copy Propagation Pass
; GCN-O1-NEXT: Post-RA pseudo instruction expansion pass
; GCN-O1-NEXT: SI Shrink Instructions
; GCN-O1-NEXT: SI post-RA bundler
; GCN-O1-NEXT: MachineDominator Tree Construction
; GCN-O1-NEXT: Machine Natural Loop Construction
@ -379,7 +380,6 @@
; GCN-O1-NEXT: SI Memory Legalizer
; GCN-O1-NEXT: MachinePostDominator Tree Construction
; GCN-O1-NEXT: SI insert wait instructions
; GCN-O1-NEXT: SI Shrink Instructions
; GCN-O1-NEXT: Insert required mode register values
; GCN-O1-NEXT: SI Insert Hard Clauses
; GCN-O1-NEXT: MachineDominator Tree Construction
@ -651,6 +651,7 @@
; GCN-O1-OPTS-NEXT: Tail Duplication
; GCN-O1-OPTS-NEXT: Machine Copy Propagation Pass
; GCN-O1-OPTS-NEXT: Post-RA pseudo instruction expansion pass
; GCN-O1-OPTS-NEXT: SI Shrink Instructions
; GCN-O1-OPTS-NEXT: SI post-RA bundler
; GCN-O1-OPTS-NEXT: MachineDominator Tree Construction
; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction
@ -663,7 +664,6 @@
; GCN-O1-OPTS-NEXT: SI Memory Legalizer
; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
; GCN-O1-OPTS-NEXT: SI insert wait instructions
; GCN-O1-OPTS-NEXT: SI Shrink Instructions
; GCN-O1-OPTS-NEXT: Insert required mode register values
; GCN-O1-OPTS-NEXT: SI Insert Hard Clauses
; GCN-O1-OPTS-NEXT: MachineDominator Tree Construction
@ -937,6 +937,7 @@
; GCN-O2-NEXT: Tail Duplication
; GCN-O2-NEXT: Machine Copy Propagation Pass
; GCN-O2-NEXT: Post-RA pseudo instruction expansion pass
; GCN-O2-NEXT: SI Shrink Instructions
; GCN-O2-NEXT: SI post-RA bundler
; GCN-O2-NEXT: MachineDominator Tree Construction
; GCN-O2-NEXT: Machine Natural Loop Construction
@ -949,7 +950,6 @@
; GCN-O2-NEXT: SI Memory Legalizer
; GCN-O2-NEXT: MachinePostDominator Tree Construction
; GCN-O2-NEXT: SI insert wait instructions
; GCN-O2-NEXT: SI Shrink Instructions
; GCN-O2-NEXT: Insert required mode register values
; GCN-O2-NEXT: SI Insert Hard Clauses
; GCN-O2-NEXT: MachineDominator Tree Construction
@ -1236,6 +1236,7 @@
; GCN-O3-NEXT: Tail Duplication
; GCN-O3-NEXT: Machine Copy Propagation Pass
; GCN-O3-NEXT: Post-RA pseudo instruction expansion pass
; GCN-O3-NEXT: SI Shrink Instructions
; GCN-O3-NEXT: SI post-RA bundler
; GCN-O3-NEXT: MachineDominator Tree Construction
; GCN-O3-NEXT: Machine Natural Loop Construction
@ -1248,7 +1249,6 @@
; GCN-O3-NEXT: SI Memory Legalizer
; GCN-O3-NEXT: MachinePostDominator Tree Construction
; GCN-O3-NEXT: SI insert wait instructions
; GCN-O3-NEXT: SI Shrink Instructions
; GCN-O3-NEXT: Insert required mode register values
; GCN-O3-NEXT: SI Insert Hard Clauses
; GCN-O3-NEXT: MachineDominator Tree Construction