forked from OSchip/llvm-project
Revert "Merge memtag instructions with adjacent stack slots."
*** Bad machine code: Tied use must be a register ***
- function: stg_alloca17
- basic block: %bb.0 entry (0x20076710580)
- instruction: early-clobber %0:gpr64common, early-clobber %1:gpr64sp = STGloop 272, %stack.0.a :: (store 272 into %ir.a, align 16)
- operand 3: %stack.0.a
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/21481/steps/test-check-all/logs/stdio
This reverts commit b675a7628c.
This commit is contained in:
Evgenii Stepanov
parent
28b9cdd260
commit
58deb20dd2
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@ -309,13 +309,6 @@ public:
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RegScavenger *RS = nullptr) const {
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}
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/// processFunctionBeforeFrameIndicesReplaced - This method is called
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/// immediately before MO_FrameIndex operands are eliminated, but after the
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/// frame is finalized. This method is optional.
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virtual void
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processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF,
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RegScavenger *RS = nullptr) const {}
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virtual unsigned getWinEHParentFrameOffset(const MachineFunction &MF) const {
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report_fatal_error("WinEH not implemented for this target");
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}
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@ -259,10 +259,6 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
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for (auto &I : EntryDbgValues)
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I.first->insert(I.first->begin(), I.second.begin(), I.second.end());
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// Allow the target machine to make final modifications to the function
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// before the frame layout is finalized.
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TFI->processFunctionBeforeFrameIndicesReplaced(MF, RS);
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// Replace all MO_FrameIndex operands with physical register references
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// and actual offsets.
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//
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@ -349,38 +349,22 @@ bool AArch64ExpandPseudo::expandSetTagLoop(
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MachineBasicBlock::iterator &NextMBBI) {
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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Register SizeReg = MI.getOperand(0).getReg();
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Register AddressReg = MI.getOperand(1).getReg();
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Register SizeReg = MI.getOperand(2).getReg();
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Register AddressReg = MI.getOperand(3).getReg();
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MachineFunction *MF = MBB.getParent();
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bool ZeroData = MI.getOpcode() == AArch64::STZGloop;
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const unsigned OpCode1 =
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ZeroData ? AArch64::STZGPostIndex : AArch64::STGPostIndex;
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const unsigned OpCode2 =
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const unsigned OpCode =
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ZeroData ? AArch64::STZ2GPostIndex : AArch64::ST2GPostIndex;
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unsigned Size = MI.getOperand(2).getImm();
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assert(Size > 0 && Size % 16 == 0);
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if (Size % (16 * 2) != 0) {
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BuildMI(MBB, MBBI, DL, TII->get(OpCode1), AddressReg)
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.addReg(AddressReg)
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.addReg(AddressReg)
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.addImm(1);
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Size -= 16;
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}
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MachineBasicBlock::iterator I =
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), SizeReg)
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.addImm(Size);
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expandMOVImm(MBB, I, 64);
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auto LoopBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
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MF->insert(++MBB.getIterator(), LoopBB);
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MF->insert(++LoopBB->getIterator(), DoneBB);
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BuildMI(LoopBB, DL, TII->get(OpCode2))
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BuildMI(LoopBB, DL, TII->get(OpCode))
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.addDef(AddressReg)
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.addReg(AddressReg)
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.addReg(AddressReg)
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@ -170,11 +170,6 @@ static cl::opt<bool>
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cl::desc("reverse the CSR restore sequence"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool> StackTaggingMergeSetTag(
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"stack-tagging-merge-settag",
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cl::desc("merge settag instruction in function epilog"), cl::init(true),
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cl::Hidden);
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STATISTIC(NumRedZoneFunctions, "Number of functions using red zone");
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/// This is the biggest offset to the stack pointer we can encode in aarch64
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@ -485,39 +480,6 @@ bool AArch64FrameLowering::shouldCombineCSRLocalStackBump(
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return true;
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}
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bool AArch64FrameLowering::shouldCombineCSRLocalStackBumpInEpilogue(
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MachineBasicBlock &MBB, unsigned StackBumpBytes) const {
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if (!shouldCombineCSRLocalStackBump(*MBB.getParent(), StackBumpBytes))
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return false;
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if (MBB.empty())
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return true;
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// Disable combined SP bump if the last instruction is an MTE tag store. It
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// is almost always better to merge SP adjustment into those instructions.
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MachineBasicBlock::iterator LastI = MBB.getFirstTerminator();
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MachineBasicBlock::iterator Begin = MBB.begin();
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while (LastI != Begin) {
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--LastI;
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if (LastI->isTransient())
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continue;
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if (!LastI->getFlag(MachineInstr::FrameDestroy))
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break;
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}
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switch (LastI->getOpcode()) {
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case AArch64::STGloop:
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case AArch64::STZGloop:
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case AArch64::STGOffset:
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case AArch64::STZGOffset:
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case AArch64::ST2GOffset:
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case AArch64::STZ2GOffset:
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return false;
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default:
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return true;
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}
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llvm_unreachable("unreachable");
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}
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// Given a load or a store instruction, generate an appropriate unwinding SEH
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// code on Windows.
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static MachineBasicBlock::iterator InsertSEH(MachineBasicBlock::iterator MBBI,
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@ -1497,7 +1459,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
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// function.
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if (MF.hasEHFunclets())
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AFI->setLocalStackSize(NumBytes - PrologueSaveSize);
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bool CombineSPBump = shouldCombineCSRLocalStackBumpInEpilogue(MBB, NumBytes);
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bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes);
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// Assume we can't combine the last pop with the sp restore.
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if (!CombineSPBump && PrologueSaveSize != 0) {
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@ -2675,399 +2637,9 @@ void AArch64FrameLowering::processFunctionBeforeFrameFinalized(
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.addImm(0);
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}
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namespace {
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struct TagStoreInstr {
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MachineInstr *MI;
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int64_t Offset, Size;
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explicit TagStoreInstr(MachineInstr *MI, int64_t Offset, int64_t Size)
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: MI(MI), Offset(Offset), Size(Size) {}
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};
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class TagStoreEdit {
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MachineFunction *MF;
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MachineBasicBlock *MBB;
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MachineRegisterInfo *MRI;
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// Tag store instructions that are being replaced.
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SmallVector<TagStoreInstr, 8> TagStores;
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// Combined memref arguments of the above instructions.
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SmallVector<MachineMemOperand *, 8> CombinedMemRefs;
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// Replace allocation tags in [FrameReg + FrameRegOffset, FrameReg +
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// FrameRegOffset + Size) with the address tag of SP.
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Register FrameReg;
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StackOffset FrameRegOffset;
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int64_t Size;
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// If not None, move FrameReg to (FrameReg + FrameRegUpdate) at the end.
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Optional<int64_t> FrameRegUpdate;
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// MIFlags for any FrameReg updating instructions.
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unsigned FrameRegUpdateFlags;
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// Use zeroing instruction variants.
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bool ZeroData;
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DebugLoc DL;
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void emitUnrolled(MachineBasicBlock::iterator InsertI);
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void emitLoop(MachineBasicBlock::iterator InsertI);
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public:
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TagStoreEdit(MachineBasicBlock *MBB, bool ZeroData)
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: MBB(MBB), ZeroData(ZeroData) {
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MF = MBB->getParent();
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MRI = &MF->getRegInfo();
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}
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// Add an instruction to be replaced. Instructions must be added in the
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// ascending order of Offset, and have to be adjacent.
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void addInstruction(TagStoreInstr I) {
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assert((TagStores.empty() ||
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TagStores.back().Offset + TagStores.back().Size == I.Offset) &&
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"Non-adjacent tag store instructions.");
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TagStores.push_back(I);
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}
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void clear() { TagStores.clear(); }
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// Emit equivalent code at the given location, and erase the current set of
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// instructions. May skip if the replacement is not profitable. May invalidate
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// the input iterator and replace it with a valid one.
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void emitCode(MachineBasicBlock::iterator &InsertI,
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const AArch64FrameLowering *TFI, bool IsLast);
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};
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void TagStoreEdit::emitUnrolled(MachineBasicBlock::iterator InsertI) {
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const AArch64InstrInfo *TII =
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MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
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const int64_t kMinOffset = -256 * 16;
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const int64_t kMaxOffset = 255 * 16;
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Register BaseReg = FrameReg;
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int64_t BaseRegOffsetBytes = FrameRegOffset.getBytes();
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if (BaseRegOffsetBytes < kMinOffset ||
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BaseRegOffsetBytes + (Size - Size % 32) > kMaxOffset) {
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Register ScratchReg = MRI->createVirtualRegister(&AArch64::GPR64RegClass);
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emitFrameOffset(*MBB, InsertI, DL, ScratchReg, BaseReg,
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{BaseRegOffsetBytes, MVT::i8}, TII);
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BaseReg = ScratchReg;
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BaseRegOffsetBytes = 0;
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}
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MachineInstr *LastI = nullptr;
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while (Size) {
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int64_t InstrSize = (Size > 16) ? 32 : 16;
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unsigned Opcode =
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InstrSize == 16
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? (ZeroData ? AArch64::STZGOffset : AArch64::STGOffset)
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: (ZeroData ? AArch64::STZ2GOffset : AArch64::ST2GOffset);
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MachineInstr *I = BuildMI(*MBB, InsertI, DL, TII->get(Opcode))
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.addReg(AArch64::SP)
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.addReg(BaseReg)
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.addImm(BaseRegOffsetBytes / 16)
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.setMemRefs(CombinedMemRefs);
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// A store to [BaseReg, #0] should go last for an opportunity to fold the
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// final SP adjustment in the epilogue.
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if (BaseRegOffsetBytes == 0)
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LastI = I;
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BaseRegOffsetBytes += InstrSize;
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Size -= InstrSize;
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}
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if (LastI)
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MBB->splice(InsertI, MBB, LastI);
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}
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void TagStoreEdit::emitLoop(MachineBasicBlock::iterator InsertI) {
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const AArch64InstrInfo *TII =
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MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
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Register BaseReg = FrameRegUpdate
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? FrameReg
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: MRI->createVirtualRegister(&AArch64::GPR64RegClass);
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Register SizeReg = MRI->createVirtualRegister(&AArch64::GPR64RegClass);
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emitFrameOffset(*MBB, InsertI, DL, BaseReg, FrameReg, FrameRegOffset, TII);
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int64_t LoopSize = Size;
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// If the loop size is not a multiple of 32, split off one 16-byte store at
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// the end to fold BaseReg update into.
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if (FrameRegUpdate && *FrameRegUpdate)
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LoopSize -= LoopSize % 32;
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MachineInstr *LoopI =
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BuildMI(*MBB, InsertI, DL,
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TII->get(ZeroData ? AArch64::STZGloop : AArch64::STGloop))
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.addDef(SizeReg)
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.addDef(BaseReg)
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.addImm(LoopSize)
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.addReg(BaseReg)
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.setMemRefs(CombinedMemRefs);
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if (FrameRegUpdate)
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LoopI->setFlags(FrameRegUpdateFlags);
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int64_t ExtraBaseRegUpdate =
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FrameRegUpdate ? (*FrameRegUpdate - FrameRegOffset.getBytes() - Size) : 0;
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if (LoopSize < Size) {
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assert(FrameRegUpdate);
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assert(Size - LoopSize == 16);
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// Tag 16 more bytes at BaseReg and update BaseReg.
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BuildMI(*MBB, InsertI, DL,
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TII->get(ZeroData ? AArch64::STZGPostIndex : AArch64::STGPostIndex))
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.addDef(BaseReg)
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.addReg(BaseReg)
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.addReg(BaseReg)
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.addImm(1 + ExtraBaseRegUpdate / 16)
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.setMemRefs(CombinedMemRefs)
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.setMIFlags(FrameRegUpdateFlags);
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} else if (ExtraBaseRegUpdate) {
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// Update BaseReg.
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BuildMI(
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*MBB, InsertI, DL,
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TII->get(ExtraBaseRegUpdate > 0 ? AArch64::ADDXri : AArch64::SUBXri))
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.addDef(BaseReg)
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.addReg(BaseReg)
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.addImm(std::abs(ExtraBaseRegUpdate))
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.addImm(0)
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.setMIFlags(FrameRegUpdateFlags);
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}
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}
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// Check if *II is a register update that can be merged into STGloop that ends
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// at (Reg + Size). RemainingOffset is the required adjustment to Reg after the
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// end of the loop.
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bool canMergeRegUpdate(MachineBasicBlock::iterator II, unsigned Reg,
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int64_t Size, int64_t *TotalOffset) {
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MachineInstr &MI = *II;
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if ((MI.getOpcode() == AArch64::ADDXri ||
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MI.getOpcode() == AArch64::SUBXri) &&
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MI.getOperand(0).getReg() == Reg && MI.getOperand(1).getReg() == Reg) {
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unsigned Shift = AArch64_AM::getShiftValue(MI.getOperand(3).getImm());
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int64_t Offset = MI.getOperand(2).getImm() << Shift;
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if (MI.getOpcode() == AArch64::SUBXri)
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Offset = -Offset;
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int64_t AbsPostOffset = std::abs(Offset - Size);
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const int64_t kMaxOffset =
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0xFFF; // Max encoding for unshifted ADDXri / SUBXri
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if (AbsPostOffset <= kMaxOffset && AbsPostOffset % 16 == 0) {
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*TotalOffset = Offset;
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return true;
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}
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}
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return false;
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}
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void mergeMemRefs(const SmallVectorImpl<TagStoreInstr> &TSE,
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SmallVectorImpl<MachineMemOperand *> &MemRefs) {
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MemRefs.clear();
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for (auto &TS : TSE) {
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MachineInstr *MI = TS.MI;
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// An instruction without memory operands may access anything. Be
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// conservative and return an empty list.
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if (MI->memoperands_empty()) {
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MemRefs.clear();
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return;
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}
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MemRefs.append(MI->memoperands_begin(), MI->memoperands_end());
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}
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}
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void TagStoreEdit::emitCode(MachineBasicBlock::iterator &InsertI,
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const AArch64FrameLowering *TFI, bool IsLast) {
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if (TagStores.empty())
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return;
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TagStoreInstr &FirstTagStore = TagStores[0];
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TagStoreInstr &LastTagStore = TagStores[TagStores.size() - 1];
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Size = LastTagStore.Offset - FirstTagStore.Offset + LastTagStore.Size;
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DL = TagStores[0].MI->getDebugLoc();
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unsigned Reg;
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FrameRegOffset = TFI->resolveFrameOffsetReference(
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*MF, FirstTagStore.Offset, false /*isFixed*/, false /*isSVE*/, Reg,
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/*PreferFP=*/false, /*ForSimm=*/true);
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FrameReg = Reg;
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FrameRegUpdate = None;
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mergeMemRefs(TagStores, CombinedMemRefs);
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LLVM_DEBUG(dbgs() << "Replacing adjacent STG instructions:\n";
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for (const auto &Instr
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: TagStores) { dbgs() << " " << *Instr.MI; });
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// Size threshold where a loop becomes shorter than a linear sequence of
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// tagging instructions.
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const int kSetTagLoopThreshold = 176;
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if (Size < kSetTagLoopThreshold) {
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if (TagStores.size() < 2)
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return;
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emitUnrolled(InsertI);
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} else {
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MachineInstr *UpdateInstr = nullptr;
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int64_t TotalOffset;
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if (IsLast) {
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// See if we can merge base register update into the STGloop.
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// This is done in AArch64LoadStoreOptimizer for "normal" stores,
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// but STGloop is way too unusual for that, and also it only
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// realistically happens in function epilogue. Also, STGloop is expanded
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// before that pass.
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if (InsertI != MBB->end() &&
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canMergeRegUpdate(InsertI, FrameReg, FrameRegOffset.getBytes() + Size,
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&TotalOffset)) {
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UpdateInstr = &*InsertI++;
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LLVM_DEBUG(dbgs() << "Folding SP update into loop:\n "
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<< *UpdateInstr);
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}
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}
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if (!UpdateInstr && TagStores.size() < 2)
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return;
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|
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if (UpdateInstr) {
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FrameRegUpdate = TotalOffset;
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FrameRegUpdateFlags = UpdateInstr->getFlags();
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}
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emitLoop(InsertI);
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if (UpdateInstr)
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UpdateInstr->eraseFromParent();
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}
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|
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for (auto &TS : TagStores)
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TS.MI->eraseFromParent();
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}
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bool isMergeableStackTaggingInstruction(MachineInstr &MI, int64_t &Offset,
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int64_t &Size, bool &ZeroData) {
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MachineFunction &MF = *MI.getParent()->getParent();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Opcode = MI.getOpcode();
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ZeroData = (Opcode == AArch64::STZGloop || Opcode == AArch64::STZGOffset ||
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Opcode == AArch64::STZ2GOffset);
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|
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if (Opcode == AArch64::STGloop || Opcode == AArch64::STZGloop) {
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if (!MI.getOperand(0).isDead() || !MI.getOperand(1).isDead())
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return false;
|
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if (!MI.getOperand(2).isImm() || !MI.getOperand(3).isFI())
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return false;
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Offset = MFI.getObjectOffset(MI.getOperand(3).getIndex());
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Size = MI.getOperand(2).getImm();
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return true;
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}
|
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|
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if (Opcode == AArch64::STGOffset || Opcode == AArch64::STZGOffset)
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Size = 16;
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else if (Opcode == AArch64::ST2GOffset || Opcode == AArch64::STZ2GOffset)
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Size = 32;
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else
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return false;
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|
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if (MI.getOperand(0).getReg() != AArch64::SP || !MI.getOperand(1).isFI())
|
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return false;
|
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Offset = MFI.getObjectOffset(MI.getOperand(1).getIndex()) +
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16 * MI.getOperand(2).getImm();
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return true;
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}
|
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|
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// Detect a run of memory tagging instructions for adjacent stack frame slots,
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// and replace them with a shorter instruction sequence:
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// * replace STG + STG with ST2G
|
||||
// * replace STGloop + STGloop with STGloop
|
||||
// This code needs to run when stack slot offsets are already known, but before
|
||||
// FrameIndex operands in STG instructions are eliminated.
|
||||
MachineBasicBlock::iterator tryMergeAdjacentSTG(MachineBasicBlock::iterator II,
|
||||
const AArch64FrameLowering *TFI,
|
||||
RegScavenger *RS) {
|
||||
bool FirstZeroData;
|
||||
int64_t Size, Offset;
|
||||
MachineInstr &MI = *II;
|
||||
MachineBasicBlock *MBB = MI.getParent();
|
||||
MachineBasicBlock::iterator NextI = ++II;
|
||||
if (&MI == &MBB->instr_back())
|
||||
return II;
|
||||
if (!isMergeableStackTaggingInstruction(MI, Offset, Size, FirstZeroData))
|
||||
return II;
|
||||
|
||||
SmallVector<TagStoreInstr, 4> Instrs;
|
||||
Instrs.emplace_back(&MI, Offset, Size);
|
||||
|
||||
constexpr int kScanLimit = 10;
|
||||
int Count = 0;
|
||||
for (MachineBasicBlock::iterator E = MBB->end();
|
||||
NextI != E && Count < kScanLimit; ++NextI) {
|
||||
MachineInstr &MI = *NextI;
|
||||
bool ZeroData;
|
||||
int64_t Size, Offset;
|
||||
// Collect instructions that update memory tags with a FrameIndex operand
|
||||
// and (when applicable) constant size, and whose output registers are dead
|
||||
// (the latter is almost always the case in practice). Since these
|
||||
// instructions effectively have no inputs or outputs, we are free to skip
|
||||
// any non-aliasing instructions in between without tracking used registers.
|
||||
if (isMergeableStackTaggingInstruction(MI, Offset, Size, ZeroData)) {
|
||||
if (ZeroData != FirstZeroData)
|
||||
break;
|
||||
Instrs.emplace_back(&MI, Offset, Size);
|
||||
continue;
|
||||
}
|
||||
|
||||
// Only count non-transient, non-tagging instructions toward the scan
|
||||
// limit.
|
||||
if (!MI.isTransient())
|
||||
++Count;
|
||||
|
||||
// Just in case, stop before the epilogue code starts.
|
||||
if (MI.getFlag(MachineInstr::FrameSetup) ||
|
||||
MI.getFlag(MachineInstr::FrameDestroy))
|
||||
break;
|
||||
|
||||
// Reject anything that may alias the collected instructions.
|
||||
if (MI.mayLoadOrStore() || MI.hasUnmodeledSideEffects())
|
||||
break;
|
||||
}
|
||||
|
||||
// New code will be inserted after the last tagging instruction we've found.
|
||||
MachineBasicBlock::iterator InsertI = Instrs.back().MI;
|
||||
InsertI++;
|
||||
|
||||
llvm::stable_sort(Instrs,
|
||||
[](const TagStoreInstr &Left, const TagStoreInstr &Right) {
|
||||
return Left.Offset < Right.Offset;
|
||||
});
|
||||
|
||||
// Make sure that we don't have any overlapping stores.
|
||||
int64_t CurOffset = Instrs[0].Offset;
|
||||
for (auto &Instr : Instrs) {
|
||||
if (CurOffset > Instr.Offset)
|
||||
return NextI;
|
||||
CurOffset = Instr.Offset + Instr.Size;
|
||||
}
|
||||
|
||||
// Find contiguous runs of tagged memory and emit shorter instruction
|
||||
// sequencies for them when possible.
|
||||
TagStoreEdit TSE(MBB, FirstZeroData);
|
||||
Optional<int64_t> EndOffset;
|
||||
for (auto &Instr : Instrs) {
|
||||
if (EndOffset && *EndOffset != Instr.Offset) {
|
||||
// Found a gap.
|
||||
TSE.emitCode(InsertI, TFI, /*IsLast = */ false);
|
||||
TSE.clear();
|
||||
}
|
||||
|
||||
TSE.addInstruction(Instr);
|
||||
EndOffset = Instr.Offset + Instr.Size;
|
||||
}
|
||||
|
||||
TSE.emitCode(InsertI, TFI, /*IsLast = */ true);
|
||||
|
||||
return InsertI;
|
||||
}
|
||||
} // namespace
|
||||
|
||||
void AArch64FrameLowering::processFunctionBeforeFrameIndicesReplaced(
|
||||
MachineFunction &MF, RegScavenger *RS = nullptr) const {
|
||||
if (StackTaggingMergeSetTag)
|
||||
for (auto &BB : MF)
|
||||
for (MachineBasicBlock::iterator II = BB.begin(); II != BB.end();)
|
||||
II = tryMergeAdjacentSTG(II, this, RS);
|
||||
}
|
||||
|
||||
/// For Win64 AArch64 EH, the offset to the Unwind object is from the SP
|
||||
/// before the update. This is easily retrieved as it is exactly the offset
|
||||
/// that is set in processFunctionBeforeFrameFinalized.
|
||||
/// For Win64 AArch64 EH, the offset to the Unwind object is from the SP before
|
||||
/// the update. This is easily retrieved as it is exactly the offset that is set
|
||||
/// in processFunctionBeforeFrameFinalized.
|
||||
int AArch64FrameLowering::getFrameIndexReferencePreferSP(
|
||||
const MachineFunction &MF, int FI, unsigned &FrameReg,
|
||||
bool IgnoreSPUpdates) const {
|
||||
|
|
|
|||
|
|
@ -77,10 +77,6 @@ public:
|
|||
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
|
||||
RegScavenger *RS) const override;
|
||||
|
||||
void
|
||||
processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF,
|
||||
RegScavenger *RS) const override;
|
||||
|
||||
unsigned getWinEHParentFrameOffset(const MachineFunction &MF) const override;
|
||||
|
||||
unsigned getWinEHFuncletFrameSize(const MachineFunction &MF) const;
|
||||
|
|
@ -111,8 +107,6 @@ private:
|
|||
int64_t assignSVEStackObjectOffsets(MachineFrameInfo &MF,
|
||||
int &MinCSFrameIndex,
|
||||
int &MaxCSFrameIndex) const;
|
||||
bool shouldCombineCSRLocalStackBumpInEpilogue(MachineBasicBlock &MBB,
|
||||
unsigned StackBumpBytes) const;
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
|
|
|||
|
|
@ -3458,8 +3458,6 @@ int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI,
|
|||
case AArch64::ST1Fourv1d:
|
||||
case AArch64::IRG:
|
||||
case AArch64::IRGstack:
|
||||
case AArch64::STGloop:
|
||||
case AArch64::STZGloop:
|
||||
return AArch64FrameOffsetCannotUpdate;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1514,17 +1514,17 @@ def TAGPstack
|
|||
// register / expression for the tagged base pointer of the current function.
|
||||
def : Pat<(int_aarch64_irg_sp i64:$Rm), (IRGstack SP, i64:$Rm)>;
|
||||
|
||||
// Large STG to be expanded into a loop. $sz is the size, $Rn is start address.
|
||||
// $Rn_wback is one past the end of the range. $Rm is the loop counter.
|
||||
// Large STG to be expanded into a loop. $Rm is the size, $Rn is start address.
|
||||
// $Rn_wback is one past the end of the range.
|
||||
let isCodeGenOnly=1, mayStore=1 in {
|
||||
def STGloop
|
||||
: Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn_wback), (ins i64imm:$sz, GPR64sp:$Rn),
|
||||
[], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,@earlyclobber $Rm" >,
|
||||
: Pseudo<(outs GPR64common:$Rm_wback, GPR64sp:$Rn_wback), (ins GPR64common:$Rm, GPR64sp:$Rn),
|
||||
[], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,$Rm = $Rm_wback,@earlyclobber $Rm_wback" >,
|
||||
Sched<[WriteAdr, WriteST]>;
|
||||
|
||||
def STZGloop
|
||||
: Pseudo<(outs GPR64common:$Rm, GPR64sp:$Rn_wback), (ins i64imm:$sz, GPR64sp:$Rn),
|
||||
[], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,@earlyclobber $Rm" >,
|
||||
: Pseudo<(outs GPR64common:$Rm_wback, GPR64sp:$Rn_wback), (ins GPR64common:$Rm, GPR64sp:$Rn),
|
||||
[], "$Rn = $Rn_wback,@earlyclobber $Rn_wback,$Rm = $Rm_wback,@earlyclobber $Rm_wback" >,
|
||||
Sched<[WriteAdr, WriteST]>;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -390,10 +390,6 @@ bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
|
|||
if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
|
||||
return false;
|
||||
|
||||
// If even offset 0 is illegal, we don't want a virtual base register.
|
||||
if (!isFrameOffsetLegal(MI, AArch64::SP, 0))
|
||||
return false;
|
||||
|
||||
// The offset likely isn't legal; we want to allocate a virtual base register.
|
||||
return true;
|
||||
}
|
||||
|
|
@ -449,17 +445,6 @@ void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
|
|||
(void)Done;
|
||||
}
|
||||
|
||||
static Register getScratchRegisterForInstruction(MachineInstr &MI) {
|
||||
// ST*Gloop can only have #fi in op3, and they have a constraint that
|
||||
// op1==op3. Since op1 is early-clobber, it may (and also must) be used as the
|
||||
// scratch register.
|
||||
if (MI.getOpcode() == AArch64::STGloop || MI.getOpcode() == AArch64::STZGloop)
|
||||
return MI.getOperand(1).getReg();
|
||||
else
|
||||
return MI.getMF()->getRegInfo().createVirtualRegister(
|
||||
&AArch64::GPR64RegClass);
|
||||
}
|
||||
|
||||
void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS) const {
|
||||
|
|
@ -516,7 +501,8 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// in a scratch register.
|
||||
Offset = TFI->resolveFrameIndexReference(
|
||||
MF, FrameIndex, FrameReg, /*PreferFP=*/false, /*ForSimm=*/true);
|
||||
Register ScratchReg = getScratchRegisterForInstruction(MI);
|
||||
Register ScratchReg =
|
||||
MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
|
||||
emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset,
|
||||
TII);
|
||||
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
|
||||
|
|
@ -545,7 +531,8 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// If we get here, the immediate doesn't fit into the instruction. We folded
|
||||
// as much as possible above. Handle the rest, providing a register that is
|
||||
// SP+LargeImm.
|
||||
Register ScratchReg = getScratchRegisterForInstruction(MI);
|
||||
Register ScratchReg =
|
||||
MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
|
||||
emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
|
||||
MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -125,13 +125,19 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(
|
|||
return EmitUnrolledSetTag(DAG, dl, Chain, Addr, ObjSize, BaseMemOperand,
|
||||
ZeroData);
|
||||
|
||||
const EVT ResTys[] = {MVT::i64, MVT::i64, MVT::Other};
|
||||
|
||||
if (Addr.getOpcode() == ISD::FrameIndex) {
|
||||
int FI = cast<FrameIndexSDNode>(Addr)->getIndex();
|
||||
Addr = DAG.getTargetFrameIndex(FI, MVT::i64);
|
||||
if (ObjSize % 32 != 0) {
|
||||
SDNode *St1 = DAG.getMachineNode(
|
||||
ZeroData ? AArch64::STZGPostIndex : AArch64::STGPostIndex, dl,
|
||||
{MVT::i64, MVT::Other},
|
||||
{Addr, Addr, DAG.getTargetConstant(1, dl, MVT::i64), Chain});
|
||||
DAG.setNodeMemRefs(cast<MachineSDNode>(St1), {BaseMemOperand});
|
||||
ObjSize -= 16;
|
||||
Addr = SDValue(St1, 0);
|
||||
Chain = SDValue(St1, 1);
|
||||
}
|
||||
SDValue Ops[] = {DAG.getTargetConstant(ObjSize, dl, MVT::i64), Addr, Chain};
|
||||
|
||||
const EVT ResTys[] = {MVT::i64, MVT::i64, MVT::Other};
|
||||
SDValue Ops[] = {DAG.getConstant(ObjSize, dl, MVT::i64), Addr, Chain};
|
||||
SDNode *St = DAG.getMachineNode(
|
||||
ZeroData ? AArch64::STZGloop : AArch64::STGloop, dl, ResTys, Ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,214 +0,0 @@
|
|||
; RUN: llc < %s -mtriple=aarch64 -mattr=+mte | FileCheck %s
|
||||
|
||||
declare void @use(i8* %p)
|
||||
declare void @llvm.aarch64.settag(i8* %p, i64 %a)
|
||||
declare void @llvm.aarch64.settag.zero(i8* %p, i64 %a)
|
||||
|
||||
define void @stg16_16() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg16_16:
|
||||
; CHECK: st2g sp, [sp], #32
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 16, align 16
|
||||
%b = alloca i8, i32 16, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 16)
|
||||
ret void
|
||||
}
|
||||
|
||||
define i32 @stg16_16_16_16_ret() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg16_16_16_16_ret:
|
||||
; CHECK: st2g sp, [sp, #32]
|
||||
; CHECK: st2g sp, [sp], #64
|
||||
; CHECK: mov w0, wzr
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 16, align 16
|
||||
%b = alloca i8, i32 16, align 16
|
||||
%c = alloca i8, i32 16, align 16
|
||||
%d = alloca i8, i32 16, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %d, i64 16)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define void @stg16_16_16_16() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg16_16_16_16:
|
||||
; CHECK: st2g sp, [sp, #32]
|
||||
; CHECK: st2g sp, [sp], #64
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 16, align 16
|
||||
%b = alloca i8, i32 16, align 16
|
||||
%c = alloca i8, i32 16, align 16
|
||||
%d = alloca i8, i32 16, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %d, i64 16)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @stg128_128_128_128() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg128_128_128_128:
|
||||
; CHECK: mov x8, #512
|
||||
; CHECK: st2g sp, [sp], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 128, align 16
|
||||
%b = alloca i8, i32 128, align 16
|
||||
%c = alloca i8, i32 128, align 16
|
||||
%d = alloca i8, i32 128, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %d, i64 128)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @stg16_512_16() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg16_512_16:
|
||||
; CHECK: mov x8, #544
|
||||
; CHECK: st2g sp, [sp], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 16, align 16
|
||||
%b = alloca i8, i32 512, align 16
|
||||
%c = alloca i8, i32 16, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 512)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 16)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @stg512_512_512() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg512_512_512:
|
||||
; CHECK: mov x8, #1536
|
||||
; CHECK: st2g sp, [sp], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 512, align 16
|
||||
%b = alloca i8, i32 512, align 16
|
||||
%c = alloca i8, i32 512, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 512)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 512)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 512)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @early(i1 %flag) {
|
||||
entry:
|
||||
; CHECK-LABEL: early:
|
||||
; CHECK: tbz w0, #0, [[LABEL:.LBB.*]]
|
||||
; CHECK: st2g sp, [sp, #
|
||||
; CHECK: st2g sp, [sp, #
|
||||
; CHECK: st2g sp, [sp, #
|
||||
; CHECK: [[LABEL]]:
|
||||
; CHECK: stg sp, [sp, #
|
||||
; CHECK: st2g sp, [sp], #
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 48, align 16
|
||||
%b = alloca i8, i32 48, align 16
|
||||
%c = alloca i8, i32 48, align 16
|
||||
br i1 %flag, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 48)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 48)
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 48)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @early_128_128(i1 %flag) {
|
||||
entry:
|
||||
; CHECK-LABEL: early_128_128:
|
||||
; CHECK: tbz w0, #0, [[LABEL:.LBB.*]]
|
||||
; CHECK: add x9, sp, #
|
||||
; CHECK: mov x8, #256
|
||||
; CHECK: st2g x9, [x9], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: [[LABEL]]:
|
||||
; CHECK: stg sp, [sp, #
|
||||
; CHECK: st2g sp, [sp], #
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 128, align 16
|
||||
%b = alloca i8, i32 128, align 16
|
||||
%c = alloca i8, i32 48, align 16
|
||||
br i1 %flag, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 128)
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 48)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @early_512_512(i1 %flag) {
|
||||
entry:
|
||||
; CHECK-LABEL: early_512_512:
|
||||
; CHECK: tbz w0, #0, [[LABEL:.LBB.*]]
|
||||
; CHECK: add x9, sp, #
|
||||
; CHECK: mov x8, #1024
|
||||
; CHECK: st2g x9, [x9], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: [[LABEL]]:
|
||||
; CHECK: stg sp, [sp, #
|
||||
; CHECK: st2g sp, [sp], #
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 512, align 16
|
||||
%b = alloca i8, i32 512, align 16
|
||||
%c = alloca i8, i32 48, align 16
|
||||
br i1 %flag, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 512)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 512)
|
||||
br label %if.end
|
||||
|
||||
if.end:
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 48)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Two loops of size 256; the second loop updates SP.
|
||||
define void @stg128_128_gap_128_128() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg128_128_gap_128_128:
|
||||
; CHECK: mov x9, sp
|
||||
; CHECK: mov x8, #256
|
||||
; CHECK: st2g x9, [x9], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: mov x8, #256
|
||||
; CHECK: st2g sp, [sp], #32
|
||||
; CHECK: sub x8, x8, #32
|
||||
; CHECK: cbnz x8,
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 128, align 16
|
||||
%a2 = alloca i8, i32 128, align 16
|
||||
%b = alloca i8, i32 32, align 16
|
||||
%c = alloca i8, i32 128, align 16
|
||||
%c2 = alloca i8, i32 128, align 16
|
||||
call void @use(i8* %b)
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %a2, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 128)
|
||||
call void @llvm.aarch64.settag(i8* %c2, i64 128)
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
declare void @llvm.aarch64.settag(i8* nocapture writeonly, i64) argmemonly nounwind writeonly "target-features"="+mte"
|
||||
define i32 @stg16_16_16_16_ret() "target-features"="+mte" {
|
||||
entry:
|
||||
%a = alloca i8, i32 16, align 16
|
||||
%b = alloca i8, i32 16, align 16
|
||||
%c = alloca i8, i32 16, align 16
|
||||
%d = alloca i8, i32 16, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %c, i64 16)
|
||||
call void @llvm.aarch64.settag(i8* %d, i64 16)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define void @stg16_store_128() "target-features"="+mte" {
|
||||
entry:
|
||||
%a = alloca i8, i32 16, align 16
|
||||
%b = alloca i8, i32 128, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 16)
|
||||
store i8 42, i8* %a
|
||||
call void @llvm.aarch64.settag(i8* %b, i64 128)
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
# A sequence of STG with a register copy in the middle.
|
||||
# Can be merged into ST2G + ST2G.
|
||||
# CHECK-LABEL: name:{{.*}}stg16_16_16_16_ret
|
||||
# CHECK-DAG: ST2GOffset $sp, $sp, 2
|
||||
# CHECK-DAG: ST2GOffset $sp, $sp, 0
|
||||
# CHECK-DAG: $w0 = COPY $wzr
|
||||
# CHECK-DAG: RET_ReallyLR implicit killed $w0
|
||||
|
||||
name: stg16_16_16_16_ret
|
||||
tracksRegLiveness: true
|
||||
stack:
|
||||
- { id: 0, name: a, size: 16, alignment: 16 }
|
||||
- { id: 1, name: b, size: 16, alignment: 16 }
|
||||
- { id: 2, name: c, size: 16, alignment: 16 }
|
||||
- { id: 3, name: d, size: 16, alignment: 16 }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
STGOffset $sp, %stack.0.a, 0 :: (store 16 into %ir.a)
|
||||
STGOffset $sp, %stack.1.b, 0 :: (store 16 into %ir.b)
|
||||
STGOffset $sp, %stack.2.c, 0 :: (store 16 into %ir.c)
|
||||
$w0 = COPY $wzr
|
||||
STGOffset $sp, %stack.3.d, 0 :: (store 16 into %ir.d)
|
||||
RET_ReallyLR implicit killed $w0
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
# A store in the middle prevents merging.
|
||||
# CHECK-LABEL: name:{{.*}}stg16_store_128
|
||||
# CHECK: ST2GOffset $sp, $sp, 2
|
||||
# CHECK: ST2GOffset $sp, $sp, 4
|
||||
# CHECK: ST2GOffset $sp, $sp, 6
|
||||
# CHECK: STGOffset $sp, $sp, 8
|
||||
# CHECK: STRBBui
|
||||
# CHECK: ST2GOffset $sp, $sp, 0
|
||||
# CHECK: RET_ReallyLR
|
||||
|
||||
name: stg16_store_128
|
||||
tracksRegLiveness: true
|
||||
stack:
|
||||
- { id: 0, name: a, size: 16, alignment: 16 }
|
||||
- { id: 1, name: b, size: 128, alignment: 16 }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
STGOffset $sp, %stack.0.a, 0 :: (store 16 into %ir.a)
|
||||
renamable $w8 = MOVi32imm 42
|
||||
ST2GOffset $sp, %stack.1.b, 6 :: (store 32 into %ir.b + 96, align 16)
|
||||
ST2GOffset $sp, %stack.1.b, 4 :: (store 32 into %ir.b + 64, align 16)
|
||||
ST2GOffset $sp, %stack.1.b, 2 :: (store 32 into %ir.b + 32, align 16)
|
||||
STRBBui killed renamable $w8, %stack.0.a, 0 :: (store 1 into %ir.a, align 16)
|
||||
ST2GOffset $sp, %stack.1.b, 0 :: (store 32 into %ir.b, align 16)
|
||||
RET_ReallyLR
|
||||
|
||||
...
|
||||
|
|
@ -64,8 +64,8 @@ entry:
|
|||
define void @stg17(i8* %p) {
|
||||
entry:
|
||||
; CHECK-LABEL: stg17:
|
||||
; CHECK: stg x0, [x0], #16
|
||||
; CHECK: mov {{(w|x)}}[[R:[0-9]+]], #256
|
||||
; CHECK: stg x0, [x0], #16
|
||||
; CHECK: st2g x0, [x0], #32
|
||||
; CHECK: sub x[[R]], x[[R]], #32
|
||||
; CHECK: cbnz x[[R]],
|
||||
|
|
@ -87,8 +87,8 @@ entry:
|
|||
define void @stzg17(i8* %p) {
|
||||
entry:
|
||||
; CHECK-LABEL: stzg17:
|
||||
; CHECK: stzg x0, [x0], #16
|
||||
; CHECK: mov {{w|x}}[[R:[0-9]+]], #256
|
||||
; CHECK: stzg x0, [x0], #16
|
||||
; CHECK: stz2g x0, [x0], #32
|
||||
; CHECK: sub x[[R]], x[[R]], #32
|
||||
; CHECK: cbnz x[[R]],
|
||||
|
|
@ -110,10 +110,10 @@ entry:
|
|||
define void @stg_alloca5() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg_alloca5:
|
||||
; CHECK: stg sp, [sp, #64]
|
||||
; CHECK: st2g sp, [sp, #32]
|
||||
; CHECK-NEXT: stg sp, [sp, #64]
|
||||
; CHECK-NEXT: st2g sp, [sp], #80
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: st2g sp, [sp]
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 80, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 80)
|
||||
ret void
|
||||
|
|
@ -122,11 +122,12 @@ entry:
|
|||
define void @stg_alloca17() {
|
||||
entry:
|
||||
; CHECK-LABEL: stg_alloca17:
|
||||
; CHECK: mov [[P:x[0-9]+]], sp
|
||||
; CHECK: stg [[P]], {{\[}}[[P]]{{\]}}, #16
|
||||
; CHECK: mov {{w|x}}[[R:[0-9]+]], #256
|
||||
; CHECK: st2g sp, [sp], #32
|
||||
; CHECK: st2g [[P]], {{\[}}[[P]]{{\]}}, #32
|
||||
; CHECK: sub x[[R]], x[[R]], #32
|
||||
; CHECK: cbnz x[[R]],
|
||||
; CHECK: stg sp, [sp], #16
|
||||
; CHECK: ret
|
||||
%a = alloca i8, i32 272, align 16
|
||||
call void @llvm.aarch64.settag(i8* %a, i64 272)
|
||||
|
|
|
|||
|
|
@ -210,10 +210,11 @@ entry:
|
|||
; DEFAULT: ldrb [[A:w.*]], [x{{.*}}]
|
||||
; DEFAULT: ldrb [[B:w.*]], [x{{.*}}]
|
||||
|
||||
; ALWAYS-DAG: ldg [[PA:x.*]], [x{{.*}}]
|
||||
; ALWAYS-DAG: ldrb [[B:w.*]], [sp]
|
||||
; ALWAYS-DAG: ldrb [[A:w.*]], {{\[}}[[PA]]{{\]}}
|
||||
; ALWAYS: ldg [[PA:x.*]], [x{{.*}}]
|
||||
; ALWAYS: ldrb [[B:w.*]], [sp]
|
||||
; ALWAYS: ldrb [[A:w.*]], {{\[}}[[PA]]{{\]}}
|
||||
|
||||
; COMMON: add w0, [[B]], [[A]]
|
||||
; COMMON: ret
|
||||
|
||||
; One of these allocas is closer to FP than to SP, and within 256 bytes
|
||||
|
|
|
|||
Loading…
Reference in New Issue