forked from OSchip/llvm-project
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
We can use an ORRWrs (mov) + SUBREG_TO_REG rather than a UBFX for G_ZEXT on s32->s64. This closer matches what SDAG does, and is likely more power efficient etc. (Also fixed up arm64-rev.ll which had a fallback check line which was entirely useless.) Simple example: https://godbolt.org/z/h1jKKdx5c Differential Revision: https://reviews.llvm.org/D102656
This commit is contained in:
Jessica Paquette
parent
75ea0abaae
commit
58c57e1b5f
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@ -2973,34 +2973,46 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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return selectCopy(I, TII, MRI, TRI, RBI);
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}
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// For the 32-bit -> 64-bit case, we can emit a mov (ORRWrs)
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// + SUBREG_TO_REG.
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//
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// If we are zero extending from 32 bits to 64 bits, it's possible that
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// the instruction implicitly does the zero extend for us. In that case,
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// we can just emit a SUBREG_TO_REG.
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// we only need the SUBREG_TO_REG.
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if (IsGPR && SrcSize == 32 && DstSize == 64) {
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// Unlike with the G_LOAD case, we don't want to look through copies
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// here.
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// here. (See isDef32.)
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MachineInstr *Def = MRI.getVRegDef(SrcReg);
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if (Def && isDef32(*Def)) {
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MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {})
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.addImm(0)
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.addUse(SrcReg)
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.addImm(AArch64::sub_32);
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Register SubregToRegSrc = SrcReg;
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if (!RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass,
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MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain G_ZEXT destination\n");
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return false;
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}
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if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass,
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MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain G_ZEXT source\n");
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return false;
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}
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I.eraseFromParent();
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return true;
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// Does the instruction implicitly zero extend?
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if (!Def || !isDef32(*Def)) {
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// No. Zero out using an OR.
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Register OrDst = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
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const Register ZReg = AArch64::WZR;
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MIB.buildInstr(AArch64::ORRWrs, {OrDst}, {ZReg, SrcReg}).addImm(0);
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SubregToRegSrc = OrDst;
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}
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MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {})
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.addImm(0)
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.addUse(SubregToRegSrc)
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.addImm(AArch64::sub_32);
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if (!RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass,
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MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain G_ZEXT destination\n");
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return false;
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}
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if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass,
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MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain G_ZEXT source\n");
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return false;
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}
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I.eraseFromParent();
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return true;
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}
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}
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@ -112,8 +112,8 @@ body: |
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %copy, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
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; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: TBNZW [[COPY1]], 3, %bb.1
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@ -254,8 +254,8 @@ body: |
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; CHECK: liveins: $w0, $x1
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; CHECK: %reg0:gpr32 = COPY $w0
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; CHECK: %reg1:gpr64 = COPY $x1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg0, %subreg.sub_32
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; CHECK: %ext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0
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; CHECK: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv
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; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
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; CHECK: $w0 = COPY %cmp
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@ -167,9 +167,9 @@ body: |
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; CHECK-LABEL: name: zext_s64_from_s32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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%0(s32) = COPY $w0
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%1(s64) = G_ZEXT %0
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$x0 = COPY %1(s64)
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@ -64,13 +64,13 @@ body: |
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bb.0:
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liveins: $w0
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; We should have a UBFMXri here, because isDef32 disallows copies.
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; We should have a ORRWrs here, because isDef32 disallows copies.
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; CHECK-LABEL: name: dont_fold_copy
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %copy, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
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; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(s32) = COPY $w0
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@ -88,14 +88,14 @@ body: |
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bb.0:
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liveins: $w0
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; We should have a UBFMXri here, because isDef32 disallows bitcasts.
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; We should have a ORRWrs here, because isDef32 disallows bitcasts.
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; CHECK-LABEL: name: dont_fold_bitcast
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32all = COPY $w0
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; CHECK: %bitcast1:gpr32 = COPY %copy
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %bitcast1, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %bitcast1, 0
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; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(s32) = COPY $w0
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@ -115,14 +115,14 @@ body: |
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bb.0:
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liveins: $x0
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; We should have a UBFMXri here, because isDef32 disallows truncs.
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; We should have a ORRWrs here, because isDef32 disallows truncs.
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; CHECK-LABEL: name: dont_fold_trunc
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %trunc:gpr32common = COPY %copy.sub_32
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %trunc, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %trunc, 0
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; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(s64) = COPY $x0
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@ -151,11 +151,11 @@ body: |
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: bb.2:
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; CHECK: %phi:gpr32 = PHI %copy1, %bb.0, %copy2, %bb.1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %phi, %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %phi, 0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x0
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; We should have a UBFMXri here, because isDef32 disallows phis.
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; We should have a ORRWrs here, because isDef32 disallows phis.
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bb.0:
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liveins: $w0, $w1, $w2
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@ -192,9 +192,9 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ADDWrr]], %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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@ -1,34 +1,34 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=FALLBACK,GISEL
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; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=GISEL
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; FALLBACK-NOT: remark{{.*}}test_rev_w
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; GISEL-NOT: remark{{.*}}test_rev_w
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define i32 @test_rev_w(i32 %a) nounwind {
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; CHECK-LABEL: test_rev_w:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev w0, w0
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_w:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: rev w0, w0
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_w:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: rev w0, w0
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; GISEL-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %0
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}
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; FALLBACK-NOT: remark{{.*}}test_rev_x
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; GISEL-NOT: remark{{.*}}test_rev_x
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define i64 @test_rev_x(i64 %a) nounwind {
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; CHECK-LABEL: test_rev_x:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rev x0, x0
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_x:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: rev x0, x0
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_x:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: rev x0, x0
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; GISEL-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %0
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@ -43,12 +43,12 @@ define i32 @test_rev_w_srl16(i16 %a) {
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_w_srl16:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: and w8, w0, #0xffff
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; FALLBACK-NEXT: rev w8, w8
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; FALLBACK-NEXT: lsr w0, w8, #16
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_w_srl16:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: and w8, w0, #0xffff
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; GISEL-NEXT: rev w8, w8
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; GISEL-NEXT: lsr w0, w8, #16
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; GISEL-NEXT: ret
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entry:
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%0 = zext i16 %a to i32
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%1 = tail call i32 @llvm.bswap.i32(i32 %0)
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@ -64,12 +64,12 @@ define i32 @test_rev_w_srl16_load(i16 *%a) {
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; CHECK-NEXT: lsr w0, w8, #16
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_w_srl16_load:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: ldrh w8, [x0]
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; FALLBACK-NEXT: rev w8, w8
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; FALLBACK-NEXT: lsr w0, w8, #16
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_w_srl16_load:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: ldrh w8, [x0]
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; GISEL-NEXT: rev w8, w8
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; GISEL-NEXT: lsr w0, w8, #16
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; GISEL-NEXT: ret
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entry:
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%0 = load i16, i16 *%a
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%1 = zext i16 %0 to i32
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@ -86,13 +86,13 @@ define i32 @test_rev_w_srl16_add(i8 %a, i8 %b) {
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; CHECK-NEXT: rev16 w0, w8
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_w_srl16_add:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: and w8, w1, #0xff
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; FALLBACK-NEXT: add w8, w8, w0, uxtb
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; FALLBACK-NEXT: rev w8, w8
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; FALLBACK-NEXT: lsr w0, w8, #16
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_w_srl16_add:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: and w8, w1, #0xff
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; GISEL-NEXT: add w8, w8, w0, uxtb
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; GISEL-NEXT: rev w8, w8
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; GISEL-NEXT: lsr w0, w8, #16
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; GISEL-NEXT: ret
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entry:
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%0 = zext i8 %a to i32
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%1 = zext i8 %b to i32
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@ -112,13 +112,12 @@ define i64 @test_rev_x_srl32(i32 %a) {
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; CHECK-NEXT: lsr x0, x8, #32
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_x_srl32:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: // kill: def $w0 killed $w0 def $x0
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; FALLBACK-NEXT: ubfx x8, x0, #0, #32
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; FALLBACK-NEXT: rev x8, x8
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; FALLBACK-NEXT: lsr x0, x8, #32
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_x_srl32:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: mov w8, w0
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; GISEL-NEXT: rev x8, x8
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; GISEL-NEXT: lsr x0, x8, #32
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; GISEL-NEXT: ret
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entry:
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%0 = zext i32 %a to i64
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%1 = tail call i64 @llvm.bswap.i64(i64 %0)
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@ -134,12 +133,12 @@ define i64 @test_rev_x_srl32_load(i32 *%a) {
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; CHECK-NEXT: lsr x0, x8, #32
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; CHECK-NEXT: ret
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;
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; FALLBACK-LABEL: test_rev_x_srl32_load:
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; FALLBACK: // %bb.0: // %entry
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; FALLBACK-NEXT: ldr w8, [x0]
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; FALLBACK-NEXT: rev x8, x8
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; FALLBACK-NEXT: lsr x0, x8, #32
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; FALLBACK-NEXT: ret
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; GISEL-LABEL: test_rev_x_srl32_load:
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; GISEL: // %bb.0: // %entry
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; GISEL-NEXT: ldr w8, [x0]
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; GISEL-NEXT: rev x8, x8
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; GISEL-NEXT: lsr x0, x8, #32
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; GISEL-NEXT: ret
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entry:
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%0 = load i32, i32 *%a
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%1 = zext i32 %0 to i64
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|
|
@ -155,13 +154,13 @@ define i64 @test_rev_x_srl32_shift(i64 %a) {
|
|||
; CHECK-NEXT: rev32 x0, x8
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_rev_x_srl32_shift:
|
||||
; FALLBACK: // %bb.0: // %entry
|
||||
; FALLBACK-NEXT: lsl x8, x0, #33
|
||||
; FALLBACK-NEXT: lsr x8, x8, #35
|
||||
; FALLBACK-NEXT: rev x8, x8
|
||||
; FALLBACK-NEXT: lsr x0, x8, #32
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_rev_x_srl32_shift:
|
||||
; GISEL: // %bb.0: // %entry
|
||||
; GISEL-NEXT: lsl x8, x0, #33
|
||||
; GISEL-NEXT: lsr x8, x8, #35
|
||||
; GISEL-NEXT: rev x8, x8
|
||||
; GISEL-NEXT: lsr x0, x8, #32
|
||||
; GISEL-NEXT: ret
|
||||
entry:
|
||||
%0 = shl i64 %a, 33
|
||||
%1 = lshr i64 %0, 35
|
||||
|
|
@ -179,18 +178,18 @@ define i32 @test_rev16_w(i32 %X) nounwind {
|
|||
; CHECK-NEXT: rev16 w0, w0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_rev16_w:
|
||||
; FALLBACK: // %bb.0: // %entry
|
||||
; FALLBACK-NEXT: lsr w8, w0, #8
|
||||
; FALLBACK-NEXT: lsl w9, w0, #8
|
||||
; FALLBACK-NEXT: and w10, w8, #0xff0000
|
||||
; FALLBACK-NEXT: and w11, w9, #0xff000000
|
||||
; FALLBACK-NEXT: and w9, w9, #0xff00
|
||||
; FALLBACK-NEXT: orr w10, w11, w10
|
||||
; FALLBACK-NEXT: and w8, w8, #0xff
|
||||
; FALLBACK-NEXT: orr w9, w10, w9
|
||||
; FALLBACK-NEXT: orr w0, w9, w8
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_rev16_w:
|
||||
; GISEL: // %bb.0: // %entry
|
||||
; GISEL-NEXT: lsr w8, w0, #8
|
||||
; GISEL-NEXT: lsl w9, w0, #8
|
||||
; GISEL-NEXT: and w10, w8, #0xff0000
|
||||
; GISEL-NEXT: and w11, w9, #0xff000000
|
||||
; GISEL-NEXT: and w9, w9, #0xff00
|
||||
; GISEL-NEXT: orr w10, w11, w10
|
||||
; GISEL-NEXT: and w8, w8, #0xff
|
||||
; GISEL-NEXT: orr w9, w10, w9
|
||||
; GISEL-NEXT: orr w0, w9, w8
|
||||
; GISEL-NEXT: ret
|
||||
entry:
|
||||
%tmp1 = lshr i32 %X, 8
|
||||
%X15 = bitcast i32 %X to i32
|
||||
|
|
@ -215,12 +214,12 @@ define i64 @test_rev16_x(i64 %a) nounwind {
|
|||
; CHECK-NEXT: ror x0, x8, #16
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_rev16_x:
|
||||
; FALLBACK: // %bb.0: // %entry
|
||||
; FALLBACK-NEXT: rev x8, x0
|
||||
; FALLBACK-NEXT: lsl x9, x8, #48
|
||||
; FALLBACK-NEXT: orr x0, x9, x8, lsr #16
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_rev16_x:
|
||||
; GISEL: // %bb.0: // %entry
|
||||
; GISEL-NEXT: rev x8, x0
|
||||
; GISEL-NEXT: lsl x9, x8, #48
|
||||
; GISEL-NEXT: orr x0, x9, x8, lsr #16
|
||||
; GISEL-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
|
||||
%1 = lshr i64 %0, 16
|
||||
|
|
@ -235,12 +234,12 @@ define i64 @test_rev32_x(i64 %a) nounwind {
|
|||
; CHECK-NEXT: rev32 x0, x0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_rev32_x:
|
||||
; FALLBACK: // %bb.0: // %entry
|
||||
; FALLBACK-NEXT: rev x8, x0
|
||||
; FALLBACK-NEXT: lsl x9, x8, #32
|
||||
; FALLBACK-NEXT: orr x0, x9, x8, lsr #32
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_rev32_x:
|
||||
; GISEL: // %bb.0: // %entry
|
||||
; GISEL-NEXT: rev x8, x0
|
||||
; GISEL-NEXT: lsl x9, x8, #32
|
||||
; GISEL-NEXT: orr x0, x9, x8, lsr #32
|
||||
; GISEL-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
|
||||
%1 = lshr i64 %0, 32
|
||||
|
|
@ -256,11 +255,11 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.8b v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64D8:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev64.8b v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64D8:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev64.8b v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||
ret <8 x i8> %tmp2
|
||||
|
|
@ -273,11 +272,11 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.4h v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64D16:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev64.4h v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64D16:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev64.4h v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
||||
ret <4 x i16> %tmp2
|
||||
|
|
@ -290,11 +289,11 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.2s v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64D32:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev64.2s v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64D32:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev64.2s v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <2 x i32>, <2 x i32>* %A
|
||||
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
|
||||
ret <2 x i32> %tmp2
|
||||
|
|
@ -307,11 +306,11 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.2s v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64Df:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev64.2s v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64Df:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev64.2s v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <2 x float>, <2 x float>* %A
|
||||
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
|
||||
ret <2 x float> %tmp2
|
||||
|
|
@ -324,11 +323,11 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.16b v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64Q8:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr q0, [x0]
|
||||
; FALLBACK-NEXT: rev64.16b v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64Q8:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: rev64.16b v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <16 x i8>, <16 x i8>* %A
|
||||
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
|
||||
ret <16 x i8> %tmp2
|
||||
|
|
@ -341,11 +340,11 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.8h v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64Q16:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr q0, [x0]
|
||||
; FALLBACK-NEXT: rev64.8h v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64Q16:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: rev64.8h v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i16>, <8 x i16>* %A
|
||||
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
||||
ret <8 x i16> %tmp2
|
||||
|
|
@ -358,11 +357,11 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.4s v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64Q32:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr q0, [x0]
|
||||
; FALLBACK-NEXT: rev64.4s v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64Q32:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: rev64.4s v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <4 x i32>, <4 x i32>* %A
|
||||
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
||||
ret <4 x i32> %tmp2
|
||||
|
|
@ -375,11 +374,11 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.4s v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64Qf:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr q0, [x0]
|
||||
; FALLBACK-NEXT: rev64.4s v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64Qf:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: rev64.4s v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <4 x float>, <4 x float>* %A
|
||||
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
||||
ret <4 x float> %tmp2
|
||||
|
|
@ -392,11 +391,11 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
|
|||
; CHECK-NEXT: rev32.8b v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev32D8:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev32.8b v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev32D8:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev32.8b v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
||||
ret <8 x i8> %tmp2
|
||||
|
|
@ -409,11 +408,11 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
|
|||
; CHECK-NEXT: rev32.4h v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev32D16:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev32.4h v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev32D16:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev32.4h v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
||||
ret <4 x i16> %tmp2
|
||||
|
|
@ -428,8 +427,11 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
|
|||
;
|
||||
; GISEL-LABEL: test_vrev32Q8:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL: ret
|
||||
; GISEL-NEXT: adrp x8, .LCPI21_0
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI21_0]
|
||||
; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <16 x i8>, <16 x i8>* %A
|
||||
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
|
||||
ret <16 x i8> %tmp2
|
||||
|
|
@ -444,8 +446,11 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
|
|||
;
|
||||
; GISEL-LABEL: test_vrev32Q16:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL: ret
|
||||
; GISEL-NEXT: adrp x8, .LCPI22_0
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI22_0]
|
||||
; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i16>, <8 x i16>* %A
|
||||
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
||||
ret <8 x i16> %tmp2
|
||||
|
|
@ -458,11 +463,11 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
|
|||
; CHECK-NEXT: rev16.8b v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev16D8:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev16.8b v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev16D8:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev16.8b v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
|
||||
ret <8 x i8> %tmp2
|
||||
|
|
@ -477,8 +482,11 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
|
|||
;
|
||||
; GISEL-LABEL: test_vrev16Q8:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL: ret
|
||||
; GISEL-NEXT: adrp x8, .LCPI24_0
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI24_0]
|
||||
; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <16 x i8>, <16 x i8>* %A
|
||||
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
|
||||
ret <16 x i8> %tmp2
|
||||
|
|
@ -493,11 +501,11 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
|
|||
; CHECK-NEXT: rev64.8b v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64D8_undef:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: ldr d0, [x0]
|
||||
; FALLBACK-NEXT: rev64.8b v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64D8_undef:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: ldr d0, [x0]
|
||||
; GISEL-NEXT: rev64.8b v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||
ret <8 x i8> %tmp2
|
||||
|
|
@ -512,8 +520,11 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
|
|||
;
|
||||
; GISEL-LABEL: test_vrev32Q16_undef:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL: ret
|
||||
; GISEL-NEXT: adrp x8, .LCPI26_0
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI26_0]
|
||||
; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL-NEXT: ret
|
||||
%tmp1 = load <8 x i16>, <8 x i16>* %A
|
||||
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
|
||||
ret <8 x i16> %tmp2
|
||||
|
|
@ -529,13 +540,13 @@ define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst
|
|||
; CHECK-NEXT: st1.h { v0 }[6], [x1]
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev64:
|
||||
; FALLBACK: // %bb.0: // %entry
|
||||
; FALLBACK-NEXT: ldr q0, [x0]
|
||||
; FALLBACK-NEXT: add x8, x1, #2 // =2
|
||||
; FALLBACK-NEXT: st1.h { v0 }[5], [x8]
|
||||
; FALLBACK-NEXT: st1.h { v0 }[6], [x1]
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev64:
|
||||
; GISEL: // %bb.0: // %entry
|
||||
; GISEL-NEXT: ldr q0, [x0]
|
||||
; GISEL-NEXT: add x8, x1, #2 // =2
|
||||
; GISEL-NEXT: st1.h { v0 }[5], [x8]
|
||||
; GISEL-NEXT: st1.h { v0 }[6], [x1]
|
||||
; GISEL-NEXT: ret
|
||||
entry:
|
||||
%0 = bitcast <4 x i16>* %source to <8 x i16>*
|
||||
%tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
|
||||
|
|
@ -559,18 +570,18 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest
|
|||
; CHECK-NEXT: str q0, [x1, #176]
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: float_vrev64:
|
||||
; FALLBACK: // %bb.0: // %entry
|
||||
; FALLBACK-NEXT: movi d0, #0000000000000000
|
||||
; FALLBACK-NEXT: mov.s v0[1], v0[0]
|
||||
; FALLBACK-NEXT: mov.s v0[2], v0[0]
|
||||
; FALLBACK-NEXT: adrp x8, .LCPI28_0
|
||||
; FALLBACK-NEXT: mov.s v0[3], v0[0]
|
||||
; FALLBACK-NEXT: ldr q1, [x0]
|
||||
; FALLBACK-NEXT: ldr q2, [x8, :lo12:.LCPI28_0]
|
||||
; FALLBACK-NEXT: tbl.16b v0, { v0, v1 }, v2
|
||||
; FALLBACK-NEXT: str q0, [x1, #176]
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: float_vrev64:
|
||||
; GISEL: // %bb.0: // %entry
|
||||
; GISEL-NEXT: movi d0, #0000000000000000
|
||||
; GISEL-NEXT: mov.s v0[1], v0[0]
|
||||
; GISEL-NEXT: mov.s v0[2], v0[0]
|
||||
; GISEL-NEXT: adrp x8, .LCPI28_0
|
||||
; GISEL-NEXT: mov.s v0[3], v0[0]
|
||||
; GISEL-NEXT: ldr q1, [x0]
|
||||
; GISEL-NEXT: ldr q2, [x8, :lo12:.LCPI28_0]
|
||||
; GISEL-NEXT: tbl.16b v0, { v0, v1 }, v2
|
||||
; GISEL-NEXT: str q0, [x1, #176]
|
||||
; GISEL-NEXT: ret
|
||||
entry:
|
||||
%0 = bitcast float* %source to <4 x float>*
|
||||
%tmp2 = load <4 x float>, <4 x float>* %0, align 4
|
||||
|
|
@ -587,10 +598,10 @@ define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
|
|||
; CHECK-NEXT: rev32.16b v0, v0
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; FALLBACK-LABEL: test_vrev32_bswap:
|
||||
; FALLBACK: // %bb.0:
|
||||
; FALLBACK-NEXT: rev32.16b v0, v0
|
||||
; FALLBACK-NEXT: ret
|
||||
; GISEL-LABEL: test_vrev32_bswap:
|
||||
; GISEL: // %bb.0:
|
||||
; GISEL-NEXT: rev32.16b v0, v0
|
||||
; GISEL-NEXT: ret
|
||||
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
|
||||
ret <4 x i32> %bswap
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue