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[X86][SkylakeClient] Fix a bunch of instructions that were incorrectly assigned Port015 instead of Port01. 

The VEC ADD and VEC MUL units aren't present on port 5 on SkylakeClient.

llvm-svn: 328241
This commit is contained in:
Craig Topper 2018-03-22 21:10:07 +00:00
parent df82274f3c
commit 58afb4ea58
7 changed files with 158 additions and 176 deletions
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204
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -1424,47 +1424,7 @@ def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr",
"ADDSSrr",
"ADDSUBPDrr",
"ADDSUBPSrr",
"MULPDrr",
"MULPSrr",
"MULSDrr",
"MULSSrr",
"SUBPDrr",
"SUBPSrr",
"SUBSDrr",
"SUBSSrr",
"VADDPDYrr",
"VADDPDrr",
"VADDPSYrr",
"VADDPSrr",
"VADDSDrr",
"VADDSSrr",
"VADDSUBPDYrr",
"VADDSUBPDrr",
"VADDSUBPSYrr",
"VADDSUBPSrr",
"VMULPDYrr",
"VMULPDrr",
"VMULPSYrr",
"VMULPSrr",
"VMULSDrr",
"VMULSSrr",
"VSUBPDYrr",
"VSUBPDrr",
"VSUBPSYrr",
"VSUBPSrr",
"VSUBSDrr",
"VSUBSSrr")>;
def: InstRW<[SKLWriteResGroup48],
(instregex
"VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
"VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
"CMPPDrri",
"CMPPSrri",
"CMPSDrr",
"CMPSSrr",
@ -1479,6 +1439,10 @@ def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
"MIN(C?)PSrr",
"MIN(C?)SDrr",
"MIN(C?)SSrr",
"MULPDrr",
"MULPSrr",
"MULSDrr",
"MULSSrr",
"PHMINPOSUWrr",
"PMADDUBSWrr",
"PMADDWDrr",
@ -1488,6 +1452,20 @@ def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
"PMULHWrr",
"PMULLWrr",
"PMULUDQrr",
"SUBPDrr",
"SUBPSrr",
"SUBSDrr",
"SUBSSrr",
"VADDPDYrr",
"VADDPDrr",
"VADDPSYrr",
"VADDPSrr",
"VADDSDrr",
"VADDSSrr",
"VADDSUBPDYrr",
"VADDSUBPDrr",
"VADDSUBPSYrr",
"VADDSUBPSrr",
"VCMPPDYrri",
"VCMPPDrri",
"VCMPPSYrri",
@ -1512,6 +1490,12 @@ def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
"VMIN(C?)PSrr",
"VMIN(C?)SDrr",
"VMIN(C?)SSrr",
"VMULPDYrr",
"VMULPDrr",
"VMULPSYrr",
"VMULPSrr",
"VMULSDrr",
"VMULSSrr",
"VPHMINPOSUWrr",
"VPMADDUBSWYrr",
"VPMADDUBSWrr",
@ -1528,7 +1512,17 @@ def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri",
"VPMULLWYrr",
"VPMULLWrr",
"VPMULUDQYrr",
"VPMULUDQrr")>;
"VPMULUDQrr",
"VSUBPDYrr",
"VSUBPDrr",
"VSUBPSYrr",
"VSUBPSrr",
"VSUBSDrr",
"VSUBSSrr")>;
def: InstRW<[SKLWriteResGroup48],
(instregex
"VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
"VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> {
let Latency = 4;
@ -1785,7 +1779,7 @@ def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
"MMX_PSUBUSBirm",
"MMX_PSUBUSWirm")>;
def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort015]> {
def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
@ -1955,7 +1949,7 @@ def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr",
"VHSUBPSYrr",
"VHSUBPSrr")>;
def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort015]> {
def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
@ -1977,7 +1971,7 @@ def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]
}
def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
def SKLWriteResGroup81 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort01]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
@ -2137,7 +2131,7 @@ def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm",
"VUNPCKLPDrm",
"VUNPCKLPSrm")>;
def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort015]> {
def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
@ -2330,7 +2324,7 @@ def: InstRW<[SKLWriteResGroup94], (instregex "LEAVE64",
"SCASQ",
"SCASW")>;
def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015]> {
def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
@ -2399,7 +2393,7 @@ def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort015
}
def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
def SKLWriteResGroup105 : SchedWriteRes<[SKLPort015]> {
def SKLWriteResGroup105 : SchedWriteRes<[SKLPort01]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [2];
@ -2622,7 +2616,7 @@ def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm",
"MMX_PHSUBDrm",
"MMX_PHSUBWrm")>;
def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort015]> {
def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort01]> {
let Latency = 8;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
@ -2714,12 +2708,24 @@ def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {
}
def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm",
"ADDSSrm",
"CMPSDrm",
"CMPSSrm",
"MAX(C?)SDrm",
"MAX(C?)SSrm",
"MIN(C?)SDrm",
"MIN(C?)SSrm",
"MULSDrm",
"MULSSrm",
"SUBSDrm",
"SUBSSrm",
"VADDSDrm",
"VADDSSrm",
"VCMPSDrm",
"VCMPSSrm",
"VMAX(C?)SDrm",
"VMAX(C?)SSrm",
"VMIN(C?)SDrm",
"VMIN(C?)SSrm",
"VMULSDrm",
"VMULSSrm",
"VSUBSDrm",
@ -2727,30 +2733,18 @@ def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm",
def: InstRW<[SKLWriteResGroup122],
(instregex "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort015]> {
def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let Latency = 9;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup123], (instregex "CMPSDrm",
"CMPSSrm",
"CVTPS2PDrm",
"MAX(C?)SDrm",
"MAX(C?)SSrm",
"MIN(C?)SDrm",
"MIN(C?)SSrm",
def: InstRW<[SKLWriteResGroup123], (instregex "CVTPS2PDrm",
"MMX_CVTPS2PIirm",
"MMX_CVTTPS2PIirm",
"VCMPSDrm",
"VCMPSSrm",
"VCVTPH2PSrm",
"VCVTPS2PDrm",
"VMAX(C?)SDrm",
"VMAX(C?)SSrm",
"VMIN(C?)SDrm",
"VMIN(C?)SSrm")>;
"VCVTPS2PDrm")>;
def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort015]> {
def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 9;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
@ -2858,27 +2852,7 @@ def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm",
"ADDPSrm",
"ADDSUBPDrm",
"ADDSUBPSrm",
"MULPDrm",
"MULPSrm",
"SUBPDrm",
"SUBPSrm",
"VADDPDrm",
"VADDPSrm",
"VADDSUBPDrm",
"VADDSUBPSrm",
"VMULPDrm",
"VMULPSrm",
"VSUBPDrm",
"VSUBPSrm")>;
def: InstRW<[SKLWriteResGroup134],
(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>;
def SKLWriteResGroup135 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 10;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
"CMPPDrmi",
"CMPPSrmi",
"CVTDQ2PSrm",
"CVTPS2DQrm",
@ -2888,6 +2862,8 @@ def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
"MAX(C?)PSrm",
"MIN(C?)PDrm",
"MIN(C?)PSrm",
"MULPDrm",
"MULPSrm",
"PHMINPOSUWrm",
"PMADDUBSWrm",
"PMADDWDrm",
@ -2897,6 +2873,12 @@ def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
"PMULHWrm",
"PMULLWrm",
"PMULUDQrm",
"SUBPDrm",
"SUBPSrm",
"VADDPDrm",
"VADDPSrm",
"VADDSUBPDrm",
"VADDSUBPSrm",
"VCMPPDrmi",
"VCMPPSrmi",
"VCVTDQ2PSrm",
@ -2908,6 +2890,8 @@ def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
"VMAX(C?)PSrm",
"VMIN(C?)PDrm",
"VMIN(C?)PSrm",
"VMULPDrm",
"VMULPSrm",
"VPHMINPOSUWrm",
"VPMADDUBSWrm",
"VPMADDWDrm",
@ -2916,7 +2900,11 @@ def: InstRW<[SKLWriteResGroup135], (instregex "CMPPDrmi",
"VPMULHUWrm",
"VPMULHWrm",
"VPMULLWrm",
"VPMULUDQrm")>;
"VPMULUDQrm",
"VSUBPDrm",
"VSUBPSrm")>;
def: InstRW<[SKLWriteResGroup134],
(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>;
def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 10;
@ -2933,7 +2921,7 @@ def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm",
"VPTESTYrm")>;
def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 10;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
@ -3009,19 +2997,7 @@ def: InstRW<[SKLWriteResGroup147], (instregex "VADDPDYrm",
"VADDPSYrm",
"VADDSUBPDYrm",
"VADDSUBPSYrm",
"VMULPDYrm",
"VMULPSYrm",
"VSUBPDYrm",
"VSUBPSYrm")>;
def: InstRW<[SKLWriteResGroup147],
(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
def SKLWriteResGroup148 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 11;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi",
"VCMPPDYrmi",
"VCMPPSYrmi",
"VCVTDQ2PSYrm",
"VCVTPS2DQYrm",
@ -3031,6 +3007,8 @@ def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi",
"VMAX(C?)PSYrm",
"VMIN(C?)PDYrm",
"VMIN(C?)PSYrm",
"VMULPDYrm",
"VMULPSYrm",
"VPMADDUBSWYrm",
"VPMADDWDYrm",
"VPMULDQYrm",
@ -3038,7 +3016,11 @@ def: InstRW<[SKLWriteResGroup148], (instregex "VCMPPDYrmi",
"VPMULHUWYrm",
"VPMULHWYrm",
"VPMULLWYrm",
"VPMULUDQYrm")>;
"VPMULUDQYrm",
"VSUBPDYrm",
"VSUBPSYrm")>;
def: InstRW<[SKLWriteResGroup147],
(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 11;
@ -3058,7 +3040,7 @@ def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
}
def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort015]> {
def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
let Latency = 11;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
@ -3079,7 +3061,7 @@ def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm",
"VCVTTSS2SI64rm",
"VCVTTSS2SIrm")>;
def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 11;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
@ -3139,7 +3121,7 @@ def: InstRW<[SKLWriteResGroup159], (instregex "(V?)HADDPDrm",
"(V?)HSUBPDrm",
"(V?)HSUBPSrm")>;
def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015]> {
def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 12;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
@ -3173,7 +3155,7 @@ def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
}
def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,SKLPort015]> {
def SKLWriteResGroup164 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 13;
let NumMicroOps = 4;
let ResourceCycles = [1,3];
@ -3203,7 +3185,7 @@ def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr",
"VDIVPDrr",
"VDIVSDrr")>;
def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort015]> {
def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let Latency = 14;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
@ -3244,7 +3226,7 @@ def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_FPrST0",
"DIVR_FST0r",
"DIVR_FrST0")>;
def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort015]> {
def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let Latency = 15;
let NumMicroOps = 3;
let ResourceCycles = [1,2];
@ -3259,7 +3241,7 @@ def SKLWriteResGroup172_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {
}
def: InstRW<[SKLWriteResGroup172_2], (instregex "VPMULLDYrm")>;
def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
def SKLWriteResGroup173 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 15;
let NumMicroOps = 4;
let ResourceCycles = [1,1,2];
@ -3351,7 +3333,7 @@ def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm",
"VDIVSDrm",
"VSQRTPSYm")>;
def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 19;
let NumMicroOps = 5;
let ResourceCycles = [1,1,3];
@ -3376,7 +3358,7 @@ def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23]> {
}
def: InstRW<[SKLWriteResGroup190], (instregex "(V?)DIVPDrm")>;
def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort015]> {
def SKLWriteResGroup191 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 20;
let NumMicroOps = 5;
let ResourceCycles = [1,1,3];

30
llvm/test/CodeGen/X86/avx-schedule.ll
View File

@ -949,7 +949,7 @@ define <4 x double> @test_cmppd(<4 x double> %a0, <4 x double> %a1, <4 x double>
;
; SKYLAKE-LABEL: test_cmppd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [4:0.33]
; SKYLAKE-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm1 # sched: [4:0.50]
; SKYLAKE-NEXT: vcmpeqpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: vorpd %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1015,7 +1015,7 @@ define <8 x float> @test_cmpps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a
;
; SKYLAKE-LABEL: test_cmpps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [4:0.33]
; SKYLAKE-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 # sched: [4:0.50]
; SKYLAKE-NEXT: vcmpeqps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: vorps %ymm0, %ymm1, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1146,7 +1146,7 @@ define <8 x float> @test_cvtdq2ps(<8 x i32> %a0, <8 x i32> *%a1) {
;
; SKYLAKE-LABEL: test_cvtdq2ps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcvtdq2ps %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcvtdq2ps %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %ymm1 # sched: [11:0.50]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1399,7 +1399,7 @@ define <8 x i32> @test_cvtps2dq(<8 x float> %a0, <8 x float> *%a1) {
;
; SKYLAKE-LABEL: test_cvtps2dq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcvtps2dq %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcvtps2dq %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcvtps2dq (%rdi), %ymm1 # sched: [11:0.50]
; SKYLAKE-NEXT: vorpd %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1463,7 +1463,7 @@ define <8 x i32> @test_cvttps2dq(<8 x float> %a0, <8 x float> *%a1) {
;
; SKYLAKE-LABEL: test_cvttps2dq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcvttps2dq %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcvttps2dq %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcvttps2dq (%rdi), %ymm1 # sched: [11:0.50]
; SKYLAKE-NEXT: vorps %ymm1, %ymm0, %ymm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1630,8 +1630,8 @@ define <8 x float> @test_dpps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2
;
; SKYLAKE-LABEL: test_dpps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [13:1.33]
; SKYLAKE-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [20:1.33]
; SKYLAKE-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [13:1.50]
; SKYLAKE-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [20:1.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_dpps:
@ -2328,7 +2328,7 @@ define <4 x double> @test_maxpd(<4 x double> %a0, <4 x double> %a1, <4 x double>
;
; SKYLAKE-LABEL: test_maxpd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmaxpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2383,7 +2383,7 @@ define <8 x float> @test_maxps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a
;
; SKYLAKE-LABEL: test_maxps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmaxps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2438,7 +2438,7 @@ define <4 x double> @test_minpd(<4 x double> %a0, <4 x double> %a1, <4 x double>
;
; SKYLAKE-LABEL: test_minpd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vminpd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vminpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vminpd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2493,7 +2493,7 @@ define <8 x float> @test_minps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a
;
; SKYLAKE-LABEL: test_minps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vminps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vminps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vminps (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4111,8 +4111,8 @@ define <4 x double> @test_roundpd(<4 x double> %a0, <4 x double> *%a1) {
;
; SKYLAKE-LABEL: test_roundpd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [8:0.67]
; SKYLAKE-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [15:0.67]
; SKYLAKE-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [8:1.00]
; SKYLAKE-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [15:1.00]
; SKYLAKE-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4175,8 +4175,8 @@ define <8 x float> @test_roundps(<8 x float> %a0, <8 x float> *%a1) {
;
; SKYLAKE-LABEL: test_roundps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [8:0.67]
; SKYLAKE-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [15:0.67]
; SKYLAKE-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [8:1.00]
; SKYLAKE-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [15:1.00]
; SKYLAKE-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;

16
llvm/test/CodeGen/X86/avx2-schedule.ll
View File

@ -3310,7 +3310,7 @@ define <16 x i16> @test_pmaddubsw(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> *%a2)
;
; SKYLAKE-LABEL: test_pmaddubsw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -3354,7 +3354,7 @@ define <8 x i32> @test_pmaddwd(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2)
;
; SKYLAKE-LABEL: test_pmaddwd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmaddwd (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4751,7 +4751,7 @@ define <4 x i64> @test_pmuldq(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> *%a2) {
;
; SKYLAKE-LABEL: test_pmuldq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4795,7 +4795,7 @@ define <16 x i16> @test_pmulhrsw(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2
;
; SKYLAKE-LABEL: test_pmulhrsw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmulhrsw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4838,7 +4838,7 @@ define <16 x i16> @test_pmulhuw(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2)
;
; SKYLAKE-LABEL: test_pmulhuw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmulhuw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4881,7 +4881,7 @@ define <16 x i16> @test_pmulhw(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2)
;
; SKYLAKE-LABEL: test_pmulhw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmulhw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -4966,7 +4966,7 @@ define <16 x i16> @test_pmullw(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2)
;
; SKYLAKE-LABEL: test_pmullw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmullw %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmullw %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmullw (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -5008,7 +5008,7 @@ define <4 x i64> @test_pmuludq(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> *%a2) {
;
; SKYLAKE-LABEL: test_pmuludq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 # sched: [11:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;

24
llvm/test/CodeGen/X86/sse-schedule.ll
View File

@ -338,7 +338,7 @@ define <4 x float> @test_cmpps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a
;
; SKYLAKE-LABEL: test_cmpps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [4:0.33]
; SKYLAKE-NEXT: vcmpeqps %xmm1, %xmm0, %xmm1 # sched: [4:0.50]
; SKYLAKE-NEXT: vcmpeqps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: vorps %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -412,7 +412,7 @@ define float @test_cmpss(float %a0, float %a1, float *%a2) {
;
; SKYLAKE-LABEL: test_cmpss:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -1299,7 +1299,7 @@ define <4 x float> @test_maxps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a
;
; SKYLAKE-LABEL: test_maxps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaxps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vmaxps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmaxps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -1366,7 +1366,7 @@ define <4 x float> @test_maxss(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a
;
; SKYLAKE-LABEL: test_maxss:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaxss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vmaxss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmaxss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -1433,7 +1433,7 @@ define <4 x float> @test_minps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a
;
; SKYLAKE-LABEL: test_minps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vminps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vminps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vminps (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -1500,7 +1500,7 @@ define <4 x float> @test_minss(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a
;
; SKYLAKE-LABEL: test_minss:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vminss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vminss %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vminss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2630,8 +2630,8 @@ define <4 x float> @test_rcpss(float %a0, float *%a1) {
; ATOM-LABEL: test_rcpss:
; ATOM: # %bb.0:
; ATOM-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:1.00]
; ATOM-NEXT: rcpss %xmm0, %xmm0
; ATOM-NEXT: rcpss %xmm1, %xmm1
; ATOM-NEXT: rcpss %xmm0, %xmm0 # sched: [0:?]
; ATOM-NEXT: rcpss %xmm1, %xmm1 # sched: [0:?]
; ATOM-NEXT: addps %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50]
;
@ -2802,8 +2802,8 @@ define <4 x float> @test_rsqrtss(float %a0, float *%a1) {
; ATOM-LABEL: test_rsqrtss:
; ATOM: # %bb.0:
; ATOM-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [1:1.00]
; ATOM-NEXT: rsqrtss %xmm0, %xmm0
; ATOM-NEXT: rsqrtss %xmm1, %xmm1
; ATOM-NEXT: rsqrtss %xmm0, %xmm0 # sched: [0:?]
; ATOM-NEXT: rsqrtss %xmm1, %xmm1 # sched: [0:?]
; ATOM-NEXT: addps %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50]
;
@ -3111,8 +3111,8 @@ define <4 x float> @test_sqrtss(<4 x float> %a0, <4 x float> *%a1) {
; ATOM-LABEL: test_sqrtss:
; ATOM: # %bb.0:
; ATOM-NEXT: movaps (%rdi), %xmm1 # sched: [1:1.00]
; ATOM-NEXT: sqrtss %xmm0, %xmm0
; ATOM-NEXT: sqrtss %xmm1, %xmm1
; ATOM-NEXT: sqrtss %xmm0, %xmm0 # sched: [0:?]
; ATOM-NEXT: sqrtss %xmm1, %xmm1 # sched: [0:?]
; ATOM-NEXT: addps %xmm1, %xmm0 # sched: [5:5.00]
; ATOM-NEXT: retq # sched: [79:39.50]
;

32
llvm/test/CodeGen/X86/sse2-schedule.ll
View File

@ -413,7 +413,7 @@ define <2 x double> @test_cmppd(<2 x double> %a0, <2 x double> %a1, <2 x double>
;
; SKYLAKE-LABEL: test_cmppd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [4:0.33]
; SKYLAKE-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm1 # sched: [4:0.50]
; SKYLAKE-NEXT: vcmpeqpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: vorpd %xmm0, %xmm1, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -487,7 +487,7 @@ define double @test_cmpsd(double %a0, double %a1, double *%a2) {
;
; SKYLAKE-LABEL: test_cmpsd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -792,7 +792,7 @@ define <4 x float> @test_cvtdq2ps(<4 x i32> %a0, <4 x i32> *%a1) {
;
; SKYLAKE-LABEL: test_cvtdq2ps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcvtdq2ps %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcvtdq2ps (%rdi), %xmm1 # sched: [10:0.50]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1028,7 +1028,7 @@ define <4 x i32> @test_cvtps2dq(<4 x float> %a0, <4 x float> *%a1) {
;
; SKYLAKE-LABEL: test_cvtps2dq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcvtps2dq %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcvtps2dq (%rdi), %xmm1 # sched: [10:0.50]
; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -1759,7 +1759,7 @@ define <4 x i32> @test_cvttps2dq(<4 x float> %a0, <4 x float> *%a1) {
;
; SKYLAKE-LABEL: test_cvttps2dq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vcvttps2dq %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vcvttps2dq (%rdi), %xmm1 # sched: [10:0.50]
; SKYLAKE-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # sched: [1:0.33]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
@ -2297,7 +2297,7 @@ define <2 x double> @test_maxpd(<2 x double> %a0, <2 x double> %a1, <2 x double>
;
; SKYLAKE-LABEL: test_maxpd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmaxpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2364,7 +2364,7 @@ define <2 x double> @test_maxsd(<2 x double> %a0, <2 x double> %a1, <2 x double>
;
; SKYLAKE-LABEL: test_maxsd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vmaxsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2431,7 +2431,7 @@ define <2 x double> @test_minpd(<2 x double> %a0, <2 x double> %a1, <2 x double>
;
; SKYLAKE-LABEL: test_minpd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vminpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vminpd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -2498,7 +2498,7 @@ define <2 x double> @test_minsd(<2 x double> %a0, <2 x double> %a1, <2 x double>
;
; SKYLAKE-LABEL: test_minsd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vminsd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vminsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -5654,7 +5654,7 @@ define <4 x i32> @test_pmaddwd(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
;
; SKYLAKE-LABEL: test_pmaddwd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmaddwd (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -6063,7 +6063,7 @@ define <8 x i16> @test_pmulhuw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
;
; SKYLAKE-LABEL: test_pmulhuw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmulhuw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -6130,7 +6130,7 @@ define <8 x i16> @test_pmulhw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
;
; SKYLAKE-LABEL: test_pmulhw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmulhw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -6197,7 +6197,7 @@ define <8 x i16> @test_pmullw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
;
; SKYLAKE-LABEL: test_pmullw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmullw %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmullw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -6263,7 +6263,7 @@ define <2 x i64> @test_pmuludq(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
;
; SKYLAKE-LABEL: test_pmuludq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -8829,8 +8829,8 @@ define <2 x double> @test_sqrtsd(<2 x double> %a0, <2 x double> *%a1) {
; ATOM-LABEL: test_sqrtsd:
; ATOM: # %bb.0:
; ATOM-NEXT: movapd (%rdi), %xmm1 # sched: [1:1.00]
; ATOM-NEXT: sqrtsd %xmm0, %xmm0
; ATOM-NEXT: sqrtsd %xmm1, %xmm1
; ATOM-NEXT: sqrtsd %xmm0, %xmm0 # sched: [0:?]
; ATOM-NEXT: sqrtsd %xmm1, %xmm1 # sched: [0:?]
; ATOM-NEXT: addpd %xmm1, %xmm0 # sched: [6:3.00]
; ATOM-NEXT: retq # sched: [79:39.50]
;

24
llvm/test/CodeGen/X86/sse41-schedule.ll
View File

@ -379,8 +379,8 @@ define <4 x float> @test_dpps(<4 x float> %a0, <4 x float> %a1, <4 x float> *%a2
;
; SKYLAKE-LABEL: test_dpps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [13:1.33]
; SKYLAKE-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [19:1.33]
; SKYLAKE-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [13:1.50]
; SKYLAKE-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [19:1.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_dpps:
@ -1189,7 +1189,7 @@ define <8 x i16> @test_phminposuw(<8 x i16> *%a0) {
; SKYLAKE-LABEL: test_phminposuw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vphminposuw (%rdi), %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: vphminposuw %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vphminposuw %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_phminposuw:
@ -2791,7 +2791,7 @@ define <2 x i64> @test_pmuldq(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> *%a2) {
;
; SKYLAKE-LABEL: test_pmuldq:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -3017,8 +3017,8 @@ define <2 x double> @test_roundpd(<2 x double> %a0, <2 x double> *%a1) {
;
; SKYLAKE-LABEL: test_roundpd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vroundpd $7, %xmm0, %xmm0 # sched: [8:0.67]
; SKYLAKE-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [14:0.67]
; SKYLAKE-NEXT: vroundpd $7, %xmm0, %xmm0 # sched: [8:1.00]
; SKYLAKE-NEXT: vroundpd $7, (%rdi), %xmm1 # sched: [14:1.00]
; SKYLAKE-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -3089,8 +3089,8 @@ define <4 x float> @test_roundps(<4 x float> %a0, <4 x float> *%a1) {
;
; SKYLAKE-LABEL: test_roundps:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vroundps $7, %xmm0, %xmm0 # sched: [8:0.67]
; SKYLAKE-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [14:0.67]
; SKYLAKE-NEXT: vroundps $7, %xmm0, %xmm0 # sched: [8:1.00]
; SKYLAKE-NEXT: vroundps $7, (%rdi), %xmm1 # sched: [14:1.00]
; SKYLAKE-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -3162,8 +3162,8 @@ define <2 x double> @test_roundsd(<2 x double> %a0, <2 x double> %a1, <2 x doubl
;
; SKYLAKE-LABEL: test_roundsd:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]
; SKYLAKE-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]
; SKYLAKE-NEXT: vroundsd $7, %xmm1, %xmm0, %xmm1 # sched: [8:1.00]
; SKYLAKE-NEXT: vroundsd $7, (%rdi), %xmm0, %xmm0 # sched: [14:1.00]
; SKYLAKE-NEXT: vaddpd %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -3235,8 +3235,8 @@ define <4 x float> @test_roundss(<4 x float> %a0, <4 x float> %a1, <4 x float> *
;
; SKYLAKE-LABEL: test_roundss:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [8:0.67]
; SKYLAKE-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [14:0.67]
; SKYLAKE-NEXT: vroundss $7, %xmm1, %xmm0, %xmm1 # sched: [8:1.00]
; SKYLAKE-NEXT: vroundss $7, (%rdi), %xmm0, %xmm0 # sched: [14:1.00]
; SKYLAKE-NEXT: vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;

4
llvm/test/CodeGen/X86/ssse3-schedule.ll
View File

@ -760,7 +760,7 @@ define <8 x i16> @test_pmaddubsw(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) {
;
; SKYLAKE-LABEL: test_pmaddubsw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
@ -828,7 +828,7 @@ define <8 x i16> @test_pmulhrsw(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
;
; SKYLAKE-LABEL: test_pmulhrsw:
; SKYLAKE: # %bb.0:
; SKYLAKE-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
; SKYLAKE-NEXT: vpmulhrsw %xmm1, %xmm0, %xmm0 # sched: [4:0.50]
; SKYLAKE-NEXT: vpmulhrsw (%rdi), %xmm0, %xmm0 # sched: [10:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;