forked from OSchip/llvm-project
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
Where the instruction mnemonic contains a dot, we name the corresponding instruction in the .td file using a _ in the place of the dot. e.g. LR_W rather than LRW. This commit updates RISCVInstrInfoZb.td to follow that convention.
This commit is contained in:
Alex Bradbury
parent
5f856c5b30
commit
588f121ada
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@ -2266,8 +2266,8 @@ void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
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if (Inst.Opc == RISCV::LUI) {
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emitToStreamer(
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Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
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} else if (Inst.Opc == RISCV::ADDUW) {
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emitToStreamer(Out, MCInstBuilder(RISCV::ADDUW)
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} else if (Inst.Opc == RISCV::ADD_UW) {
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emitToStreamer(Out, MCInstBuilder(RISCV::ADD_UW)
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.addReg(DestReg)
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.addReg(SrcReg)
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.addReg(RISCV::X0));
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@ -31,7 +31,7 @@ static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
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case RISCV::LUI:
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Compressed = isInt<6>(Instr.Imm);
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break;
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case RISCV::ADDUW:
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case RISCV::ADD_UW:
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Compressed = false;
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break;
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}
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@ -123,10 +123,11 @@ static void generateInstSeqImpl(int64_t Val,
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}
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}
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// Try to use SLLIUW for Hi52 when it is uint32 but not int32.
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// Try to use SLLI_UW for Hi52 when it is uint32 but not int32.
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if (isUInt<32>((uint64_t)Hi52) && !isInt<32>((uint64_t)Hi52) &&
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ActiveFeatures[RISCV::FeatureStdExtZba]) {
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// Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with SLLIUW.
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// Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
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// SLLI_UW.
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Hi52 = ((uint64_t)Hi52) | (0xffffffffull << 32);
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Unsigned = true;
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}
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@ -134,7 +135,7 @@ static void generateInstSeqImpl(int64_t Val,
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generateInstSeqImpl(Hi52, ActiveFeatures, Res);
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if (Unsigned)
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Res.push_back(RISCVMatInt::Inst(RISCV::SLLIUW, ShiftAmount));
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Res.push_back(RISCVMatInt::Inst(RISCV::SLLI_UW, ShiftAmount));
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else
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Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
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if (Lo12)
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@ -210,7 +211,7 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
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uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
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TmpSeq.clear();
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generateInstSeqImpl(LeadingOnesVal, ActiveFeatures, TmpSeq);
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TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDUW, 0));
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TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADD_UW, 0));
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// Keep the new sequence if it is an improvement.
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if (TmpSeq.size() < Res.size()) {
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@ -166,8 +166,8 @@ static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
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SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
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if (Inst.Opc == RISCV::LUI)
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Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
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else if (Inst.Opc == RISCV::ADDUW)
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Result = CurDAG->getMachineNode(RISCV::ADDUW, DL, XLenVT, SrcReg,
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else if (Inst.Opc == RISCV::ADD_UW)
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Result = CurDAG->getMachineNode(RISCV::ADD_UW, DL, XLenVT, SrcReg,
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CurDAG->getRegister(RISCV::X0, XLenVT));
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else if (Inst.Opc == RISCV::SH1ADD || Inst.Opc == RISCV::SH2ADD ||
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Inst.Opc == RISCV::SH3ADD)
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@ -775,10 +775,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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C1 == (maskTrailingOnes<uint64_t>(XLen - (C2 + C3)) << C2)) {
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// Use slli.uw when possible.
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if ((XLen - (C2 + C3)) == 32 && Subtarget->hasStdExtZba()) {
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SDNode *SLLIUW =
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CurDAG->getMachineNode(RISCV::SLLIUW, DL, XLenVT, X,
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SDNode *SLLI_UW =
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CurDAG->getMachineNode(RISCV::SLLI_UW, DL, XLenVT, X,
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CurDAG->getTargetConstant(C2, DL, XLenVT));
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ReplaceNode(Node, SLLIUW);
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ReplaceNode(Node, SLLI_UW);
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return;
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}
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@ -1811,7 +1811,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
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case RISCV::CLZW:
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case RISCV::CTZW:
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case RISCV::CPOPW:
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case RISCV::SLLIUW:
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case RISCV::SLLI_UW:
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case RISCV::FCVT_H_W:
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case RISCV::FCVT_H_WU:
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case RISCV::FCVT_S_W:
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@ -1830,20 +1830,20 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
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if (Bits < (64 - countLeadingZeros(User->getConstantOperandVal(1))))
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return false;
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break;
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case RISCV::SEXTB:
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case RISCV::SEXT_B:
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if (Bits < 8)
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return false;
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break;
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case RISCV::SEXTH:
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case RISCV::ZEXTH_RV32:
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case RISCV::ZEXTH_RV64:
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case RISCV::SEXT_H:
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case RISCV::ZEXT_H_RV32:
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case RISCV::ZEXT_H_RV64:
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if (Bits < 16)
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return false;
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break;
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case RISCV::ADDUW:
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case RISCV::SH1ADDUW:
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case RISCV::SH2ADDUW:
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case RISCV::SH3ADDUW:
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case RISCV::ADD_UW:
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case RISCV::SH1ADD_UW:
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case RISCV::SH2ADD_UW:
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case RISCV::SH3ADD_UW:
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// The first operand to add.uw/shXadd.uw is implicitly zero extended from
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// 32 bits.
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if (UI.getOperandNo() != 0 || Bits < 32)
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@ -654,8 +654,8 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
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BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
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.addImm(Inst.Imm)
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.setMIFlag(Flag);
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} else if (Inst.Opc == RISCV::ADDUW) {
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDUW), Result)
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} else if (Inst.Opc == RISCV::ADD_UW) {
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BuildMI(MBB, MBBI, DL, get(RISCV::ADD_UW), Result)
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.addReg(SrcReg, RegState::Kill)
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.addReg(RISCV::X0)
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.setMIFlag(Flag);
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@ -360,13 +360,16 @@ def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
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def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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// These instructions were named xperm.n and xperm.b in the last version of
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// the draft bit manipulation specification they were included in. However, we
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// use the mnemonics given to them in the ratified Zbkx extension.
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let Predicates = [HasStdExtZbpOrZbkx] in {
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def XPERMN : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
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def XPERMB : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
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def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
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def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
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} // Predicates = [HasStdExtZbpOrZbkx]
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let Predicates = [HasStdExtZbp] in {
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def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
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def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb] in
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@ -416,37 +419,37 @@ def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
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Sched<[]>;
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let Predicates = [HasStdExtZbb] in {
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def SEXTB : RVBUnary<0b0110000, 0b00100, 0b001, OPC_OP_IMM, "sext.b">,
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Sched<[WriteIALU, ReadIALU]>;
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def SEXTH : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">,
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Sched<[WriteIALU, ReadIALU]>;
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def SEXT_B : RVBUnary<0b0110000, 0b00100, 0b001, OPC_OP_IMM, "sext.b">,
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Sched<[WriteIALU, ReadIALU]>;
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def SEXT_H : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">,
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Sched<[WriteIALU, ReadIALU]>;
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} // Predicates = [HasStdExtZbb]
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let Predicates = [HasStdExtZbr] in {
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def CRC32B : RVBUnary<0b0110000, 0b10000, 0b001, OPC_OP_IMM, "crc32.b">,
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Sched<[]>;
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def CRC32H : RVBUnary<0b0110000, 0b10001, 0b001, OPC_OP_IMM, "crc32.h">,
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Sched<[]>;
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def CRC32W : RVBUnary<0b0110000, 0b10010, 0b001, OPC_OP_IMM, "crc32.w">,
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Sched<[]>;
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def CRC32_B : RVBUnary<0b0110000, 0b10000, 0b001, OPC_OP_IMM, "crc32.b">,
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Sched<[]>;
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def CRC32_H : RVBUnary<0b0110000, 0b10001, 0b001, OPC_OP_IMM, "crc32.h">,
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Sched<[]>;
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def CRC32_W : RVBUnary<0b0110000, 0b10010, 0b001, OPC_OP_IMM, "crc32.w">,
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Sched<[]>;
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} // Predicates = [HasStdExtZbr]
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let Predicates = [HasStdExtZbr, IsRV64] in
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def CRC32D : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">,
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Sched<[]>;
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def CRC32_D : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">,
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Sched<[]>;
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let Predicates = [HasStdExtZbr] in {
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def CRC32CB : RVBUnary<0b0110000, 0b11000, 0b001, OPC_OP_IMM, "crc32c.b">,
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Sched<[]>;
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def CRC32CH : RVBUnary<0b0110000, 0b11001, 0b001, OPC_OP_IMM, "crc32c.h">,
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Sched<[]>;
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def CRC32CW : RVBUnary<0b0110000, 0b11010, 0b001, OPC_OP_IMM, "crc32c.w">,
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Sched<[]>;
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def CRC32C_B : RVBUnary<0b0110000, 0b11000, 0b001, OPC_OP_IMM, "crc32c.b">,
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Sched<[]>;
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def CRC32C_H : RVBUnary<0b0110000, 0b11001, 0b001, OPC_OP_IMM, "crc32c.h">,
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Sched<[]>;
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def CRC32C_W : RVBUnary<0b0110000, 0b11010, 0b001, OPC_OP_IMM, "crc32c.w">,
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Sched<[]>;
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} // Predicates = [HasStdExtZbr]
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let Predicates = [HasStdExtZbr, IsRV64] in
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def CRC32CD : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">,
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Sched<[]>;
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def CRC32C_D : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">,
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Sched<[]>;
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let Predicates = [HasStdExtZbc] in {
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def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">,
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@ -506,16 +509,16 @@ def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZba, IsRV64] in {
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def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
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Sched<[WriteShiftImm32, ReadShiftImm32]>;
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def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">,
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Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
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def SH1ADDUW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH2ADDUW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SLLI_UW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
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Sched<[WriteShiftImm32, ReadShiftImm32]>;
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def ADD_UW : ALUW_rr<0b0000100, 0b000, "add.uw">,
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Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
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def SH1ADD_UW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH2ADD_UW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH3ADD_UW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
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@ -531,7 +534,7 @@ def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
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def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in
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@ -585,8 +588,8 @@ def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
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let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def ZEXTH_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
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(ins GPR:$rs1), "zext.h", "$rd, $rs1">,
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def ZEXT_H_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
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(ins GPR:$rs1), "zext.h", "$rd, $rs1">,
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Sched<[WriteIALU, ReadIALU]> {
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let rs2 = 0b00000;
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}
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@ -594,8 +597,8 @@ def ZEXTH_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
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let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
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(ins GPR:$rs1), "zext.h", "$rd, $rs1">,
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def ZEXT_H_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
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(ins GPR:$rs1), "zext.h", "$rd, $rs1">,
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Sched<[WriteIALU, ReadIALU]> {
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let rs2 = 0b00000;
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}
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@ -619,8 +622,8 @@ def REV8_RV64 : RVBUnary<0b0110101, 0b11000, 0b101, OPC_OP_IMM, "rev8">,
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} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
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let Predicates = [HasStdExtZbbOrZbp] in {
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def ORCB : RVBUnary<0b0010100, 0b00111, 0b101, OPC_OP_IMM, "orc.b">,
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Sched<[WriteORCB, ReadORCB]>;
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def ORC_B : RVBUnary<0b0010100, 0b00111, 0b101, OPC_OP_IMM, "orc.b">,
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Sched<[WriteORCB, ReadORCB]>;
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} // Predicates = [HasStdExtZbbOrZbp]
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let Predicates = [HasStdExtZbpOrZbkb] in
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@ -637,7 +640,7 @@ def UNZIP_RV32 : RVBUnary<0b0000100, 0b01111, 0b101, OPC_OP_IMM, "unzip">;
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZba, IsRV64] in {
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def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
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def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
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}
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let Predicates = [HasStdExtZbp] in {
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@ -775,8 +778,8 @@ def : InstAlias<"gorcw $rd, $rs1, $shamt",
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// Zbp is unratified and that it would likely adopt the already ratified Zbkx names.
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// Thus current Zbp instructions are defined as aliases for Zbkx instructions.
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let Predicates = [HasStdExtZbp] in {
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def : InstAlias<"xperm.b $rd, $rs1, $rs2", (XPERMB GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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def : InstAlias<"xperm.n $rd, $rs1, $rs2", (XPERMN GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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def : InstAlias<"xperm.b $rd, $rs1, $rs2", (XPERM8 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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def : InstAlias<"xperm.n $rd, $rs1, $rs2", (XPERM4 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbs] in {
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@ -861,7 +864,7 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
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// We treat orc.b as a separate instruction, so match it directly. We also
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// lower the Zbb orc.b intrinsic to this.
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def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
|
||||
def : Pat<(riscv_gorc GPR:$rs1, 7), (ORC_B GPR:$rs1)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtZbp] in {
|
||||
|
|
@ -869,9 +872,9 @@ def : PatGprGpr<riscv_grev, GREV>;
|
|||
def : PatGprGpr<riscv_gorc, GORC>;
|
||||
def : PatGprGpr<riscv_shfl, SHFL>;
|
||||
def : PatGprGpr<riscv_unshfl, UNSHFL>;
|
||||
def : PatGprGpr<int_riscv_xperm_n, XPERMN>;
|
||||
def : PatGprGpr<int_riscv_xperm_b, XPERMB>;
|
||||
def : PatGprGpr<int_riscv_xperm_h, XPERMH>;
|
||||
def : PatGprGpr<int_riscv_xperm_n, XPERM4>;
|
||||
def : PatGprGpr<int_riscv_xperm_b, XPERM8>;
|
||||
def : PatGprGpr<int_riscv_xperm_h, XPERM_H>;
|
||||
def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
|
||||
def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
|
||||
def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
|
||||
|
|
@ -882,7 +885,7 @@ def : Pat<(riscv_grev GPR:$rs1, 7), (BREV8 GPR:$rs1)>;
|
|||
} // Predicates = [HasStdExtZbp]
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in
|
||||
def : PatGprGpr<int_riscv_xperm_w, XPERMW>;
|
||||
def : PatGprGpr<int_riscv_xperm_w, XPERM_W>;
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV32] in {
|
||||
def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
|
||||
|
|
@ -949,8 +952,8 @@ def : PatGpr<ctpop, CPOP>;
|
|||
} // Predicates = [HasStdExtZbb]
|
||||
|
||||
let Predicates = [HasStdExtZbb] in {
|
||||
def : Pat<(sext_inreg GPR:$rs1, i8), (SEXTB GPR:$rs1)>;
|
||||
def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>;
|
||||
def : Pat<(sext_inreg GPR:$rs1, i8), (SEXT_B GPR:$rs1)>;
|
||||
def : Pat<(sext_inreg GPR:$rs1, i16), (SEXT_H GPR:$rs1)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtZbb] in {
|
||||
|
|
@ -994,9 +997,9 @@ def : Pat<(or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)),
|
|||
} // Predicates = [HasStdExtZbpOrZbkb]
|
||||
|
||||
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
|
||||
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV32 GPR:$rs)>;
|
||||
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>;
|
||||
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
|
||||
def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV64 GPR:$rs)>;
|
||||
def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
|
||||
|
||||
// Pattern to exclude simm12 immediates from matching.
|
||||
def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
|
||||
|
|
@ -1074,24 +1077,24 @@ def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
|
|||
|
||||
let Predicates = [HasStdExtZba, IsRV64] in {
|
||||
def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
|
||||
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
|
||||
(SLLI_UW GPR:$rs1, uimm5:$shamt)>;
|
||||
def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)),
|
||||
(ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADDUW GPR:$rs, X0)>;
|
||||
(ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADD_UW GPR:$rs, X0)>;
|
||||
|
||||
def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), non_imm12:$rs2)),
|
||||
(SH1ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
(SH1ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 2)), non_imm12:$rs2)),
|
||||
(SH2ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
(SH2ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 3)), non_imm12:$rs2)),
|
||||
(SH3ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
(SH3ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 1)), 0x1FFFFFFFF), non_imm12:$rs2)),
|
||||
(SH1ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
(SH1ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 2)), 0x3FFFFFFFF), non_imm12:$rs2)),
|
||||
(SH2ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
(SH2ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2)),
|
||||
(SH3ADDUW GPR:$rs1, GPR:$rs2)>;
|
||||
(SH3ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
} // Predicates = [HasStdExtZba, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
|
||||
|
|
@ -1167,17 +1170,17 @@ def : PatGprGpr<riscv_bdecompressw, BDECOMPRESSW>;
|
|||
} // Predicates = [HasStdExtZbe, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbr] in {
|
||||
def : PatGpr<int_riscv_crc32_b, CRC32B>;
|
||||
def : PatGpr<int_riscv_crc32_h, CRC32H>;
|
||||
def : PatGpr<int_riscv_crc32_w, CRC32W>;
|
||||
def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
|
||||
def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
|
||||
def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
|
||||
def : PatGpr<int_riscv_crc32_b, CRC32_B>;
|
||||
def : PatGpr<int_riscv_crc32_h, CRC32_H>;
|
||||
def : PatGpr<int_riscv_crc32_w, CRC32_W>;
|
||||
def : PatGpr<int_riscv_crc32c_b, CRC32C_B>;
|
||||
def : PatGpr<int_riscv_crc32c_h, CRC32C_H>;
|
||||
def : PatGpr<int_riscv_crc32c_w, CRC32C_W>;
|
||||
} // Predicates = [HasStdExtZbr]
|
||||
|
||||
let Predicates = [HasStdExtZbr, IsRV64] in {
|
||||
def : PatGpr<int_riscv_crc32_d, CRC32D>;
|
||||
def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
|
||||
def : PatGpr<int_riscv_crc32_d, CRC32_D>;
|
||||
def : PatGpr<int_riscv_crc32c_d, CRC32C_D>;
|
||||
} // Predicates = [HasStdExtZbr, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbf] in
|
||||
|
|
@ -1196,6 +1199,6 @@ def : PatGpr<int_riscv_unzip, UNZIP_RV32>;
|
|||
} // Predicates = [HasStdExtZbkb, IsRV32]
|
||||
|
||||
let Predicates = [HasStdExtZbkx] in {
|
||||
def : PatGprGpr<int_riscv_xperm4, XPERMN>;
|
||||
def : PatGprGpr<int_riscv_xperm8, XPERMB>;
|
||||
def : PatGprGpr<int_riscv_xperm4, XPERM4>;
|
||||
def : PatGprGpr<int_riscv_xperm8, XPERM8>;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,9 +99,9 @@ static bool isSignExtendingOpW(const MachineInstr &MI) {
|
|||
case RISCV::SLTI:
|
||||
case RISCV::SLTU:
|
||||
case RISCV::SLTIU:
|
||||
case RISCV::SEXTB:
|
||||
case RISCV::SEXTH:
|
||||
case RISCV::ZEXTH_RV64:
|
||||
case RISCV::SEXT_B:
|
||||
case RISCV::SEXT_H:
|
||||
case RISCV::ZEXT_H_RV64:
|
||||
return true;
|
||||
// shifting right sufficiently makes the value 32-bit sign-extended
|
||||
case RISCV::SRAI:
|
||||
|
|
|
|||
Loading…
Reference in New Issue