forked from OSchip/llvm-project
[NFC][PowerPC] Add 2 new cases to test livevars pass
This commit is contained in:
Kang Zhang
parent
20de2323a0
commit
58684fbb6f
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# RUN: not --crash llc -mtriple powerpc64le-unknown-linux-gnu %s -o - 2>&1 \
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# RUN: -run-pass=livevars,phi-node-elimination -verify-machineinstrs \
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# RUN: | FileCheck %s
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--- |
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; Function Attrs: noreturn nounwind
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define signext i32 @zext_free(i8** nocapture dereferenceable(8) %p) {
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entry:
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%.pre = load i8*, i8** %p, align 8
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br label %loop
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loop: ; preds = %loop, %if.then3, %entry
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%0 = phi i8* [ %.pre, %entry ], [ %incdec.ptr4, %if.then3 ], [ %incdec.ptr, %loop ]
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%1 = load i8, i8* %0, align 1
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%tobool = icmp eq i8 %1, 0
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%incdec.ptr = getelementptr inbounds i8, i8* %0, i64 1
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store i8* %incdec.ptr, i8** %p, align 8
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%2 = load i8, i8* %incdec.ptr, align 1
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%tobool2 = icmp ne i8 %2, 0
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%or.cond = and i1 %tobool, %tobool2
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br i1 %or.cond, label %if.then3, label %loop
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if.then3: ; preds = %loop
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%incdec.ptr4 = getelementptr inbounds i8, i8* %0, i64 2
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store i8* %incdec.ptr4, i8** %p, align 8
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br label %loop
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}
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...
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---
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name: zext_free
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: g8rc, preferred-register: '' }
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- { id: 4, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 5, class: gprc, preferred-register: '' }
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- { id: 6, class: crrc, preferred-register: '' }
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- { id: 7, class: crbitrc, preferred-register: '' }
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- { id: 8, class: gprc, preferred-register: '' }
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- { id: 9, class: crrc, preferred-register: '' }
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- { id: 10, class: crbitrc, preferred-register: '' }
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- { id: 11, class: crbitrc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%4' }
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $x3
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%4:g8rc_and_g8rc_nox0 = COPY killed $x3
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%0:g8rc = LD 0, %4 :: (dereferenceable load 8 from %ir.p)
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bb.1.loop:
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successors: %bb.1(0x20000000), %bb.2(0x60000000)
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%1:g8rc_and_g8rc_nox0 = PHI %0, %bb.0, %2, %bb.1, %3, %bb.3, %2, %bb.2
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%5:gprc = LBZ 0, %1 :: (load 1 from %ir.0)
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%6:crrc = CMPWI killed %5, 0
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%7:crbitrc = COPY killed %6.sub_eq
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%2:g8rc = nuw ADDI8 %1, 1
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STD %2, 0, %4 :: (store 8 into %ir.p)
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%8:gprc = LBZ 1, %1 :: (load 1 from %ir.incdec.ptr)
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BCn killed %7, %bb.1
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B %bb.2
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bb.2.loop:
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successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
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%9:crrc = CMPWI killed %8, 0
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%10:crbitrc = COPY killed %9.sub_eq
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BC killed %10, %bb.1
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B %bb.3
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bb.3.if.then3:
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successors: %bb.1(0x80000000)
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%3:g8rc = nuw ADDI8 killed %1, 2
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STD %3, 0, %4 :: (store 8 into %ir.p)
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B %bb.1
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...
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# CHECK-LABEL: Bad machine code: LiveVariables: Block should not be in AliveBlocks
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# CHECK-NEXT: - function: zext_free
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# CHECK-NEXT: - basic block: %bb.2 loop
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# CHECK-NEXT: Virtual register %2 is not needed live through the block.
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# CHECK-NEXT: LLVM ERROR: Found 1 machine code errors.
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@ -0,0 +1,195 @@
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# RUN: not --crash llc -mtriple powerpc64le-unknown-linux-gnu %s -o - 2>&1 \
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# RUN: -run-pass=livevars,phi-node-elimination -verify-machineinstrs \
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# RUN: | FileCheck %s
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--- |
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define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) {
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entry:
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%cmp1 = fcmp oeq float %c3, %c4
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%cmp3tmp = fcmp oeq float %c1, %c2
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%cmp3 = icmp slt i1 %cmp3tmp, %cmp1
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%cond = select i1 %cmp3, float %a1, float %a2
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ret float %cond
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}
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define signext i32 @select-i1-vs-i1(i8** nocapture dereferenceable(8) %p) #0 {
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entry:
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%.pre = load i8*, i8** %p, align 8
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br label %loop
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loop: ; preds = %loop, %if.then3, %entry
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%0 = phi i8* [ %.pre, %entry ], [ %incdec.ptr4, %if.then3 ], [ %incdec.ptr, %loop ]
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%1 = load i8, i8* %0, align 1
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%tobool = icmp eq i8 %1, 0
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%incdec.ptr = getelementptr inbounds i8, i8* %0, i64 1
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store i8* %incdec.ptr, i8** %p, align 8
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%2 = load i8, i8* %incdec.ptr, align 1
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%tobool2 = icmp ne i8 %2, 0
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%or.cond = and i1 %tobool, %tobool2
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br i1 %or.cond, label %if.then3, label %loop
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if.then3: ; preds = %loop
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%incdec.ptr4 = getelementptr inbounds i8, i8* %0, i64 2
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store i8* %incdec.ptr4, i8** %p, align 8
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br label %loop
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}
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...
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---
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name: testfloatslt
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tracksRegLiveness: true
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registers:
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- { id: 0, class: f4rc, preferred-register: '' }
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- { id: 1, class: f4rc, preferred-register: '' }
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- { id: 2, class: f4rc, preferred-register: '' }
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- { id: 3, class: f4rc, preferred-register: '' }
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- { id: 4, class: f4rc, preferred-register: '' }
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- { id: 5, class: f4rc, preferred-register: '' }
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- { id: 6, class: crrc, preferred-register: '' }
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- { id: 7, class: crbitrc, preferred-register: '' }
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- { id: 8, class: crrc, preferred-register: '' }
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- { id: 9, class: crbitrc, preferred-register: '' }
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- { id: 10, class: crbitrc, preferred-register: '' }
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- { id: 11, class: f4rc, preferred-register: '' }
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liveins:
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- { reg: '$f1', virtual-reg: '%0' }
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- { reg: '$f2', virtual-reg: '%1' }
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- { reg: '$f3', virtual-reg: '%2' }
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- { reg: '$f4', virtual-reg: '%3' }
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- { reg: '$f5', virtual-reg: '%4' }
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- { reg: '$f6', virtual-reg: '%5' }
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body: |
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bb.0.entry:
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successors: %bb.2(0x20000000), %bb.1(0x60000000)
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liveins: $f1, $f2, $f3, $f4, $f5, $f6
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%5:f4rc = COPY killed $f6
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%4:f4rc = COPY killed $f5
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%3:f4rc = COPY killed $f4
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%2:f4rc = COPY killed $f3
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%1:f4rc = COPY killed $f2
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%0:f4rc = COPY killed $f1
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%6:crrc = FCMPUS killed %2, killed %3
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%7:crbitrc = COPY killed %6.sub_eq
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BC killed %7, %bb.2
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B %bb.1
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bb.1.entry:
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successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555)
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%8:crrc = FCMPUS killed %0, killed %1
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%9:crbitrc = COPY killed %8.sub_eq
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BC killed %9, %bb.3
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bb.2.entry:
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successors: %bb.3(0x80000000)
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bb.3.entry:
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%11:f4rc = PHI %5, %bb.2, %4, %bb.1
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$f1 = COPY killed %11
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BLR8 implicit $lr8, implicit $rm, implicit killed $f1
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...
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---
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name: select-i1-vs-i1
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: g8rc, preferred-register: '' }
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- { id: 4, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 5, class: gprc, preferred-register: '' }
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- { id: 6, class: crrc, preferred-register: '' }
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- { id: 7, class: crbitrc, preferred-register: '' }
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- { id: 8, class: gprc, preferred-register: '' }
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- { id: 9, class: crrc, preferred-register: '' }
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- { id: 10, class: crbitrc, preferred-register: '' }
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- { id: 11, class: crbitrc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%4' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $x3
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%4:g8rc_and_g8rc_nox0 = COPY killed $x3
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%0:g8rc = LD 0, %4 :: (dereferenceable load 8 from %ir.p)
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bb.1.loop:
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successors: %bb.1(0x20000000), %bb.2(0x60000000)
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%1:g8rc_and_g8rc_nox0 = PHI %0, %bb.0, %2, %bb.1, %3, %bb.3, %2, %bb.2
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%5:gprc = LBZ 0, %1 :: (load 1 from %ir.0)
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%6:crrc = CMPWI killed %5, 0
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%7:crbitrc = COPY killed %6.sub_eq
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%2:g8rc = nuw ADDI8 %1, 1
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STD %2, 0, %4 :: (store 8 into %ir.p)
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%8:gprc = LBZ 1, %1 :: (load 1 from %ir.incdec.ptr)
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BCn killed %7, %bb.1
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B %bb.2
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bb.2.loop:
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successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
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%9:crrc = CMPWI killed %8, 0
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%10:crbitrc = COPY killed %9.sub_eq
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BC killed %10, %bb.1
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B %bb.3
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bb.3.if.then3:
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successors: %bb.1(0x80000000)
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%3:g8rc = nuw ADDI8 killed %1, 2
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STD %3, 0, %4 :: (store 8 into %ir.p)
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B %bb.1
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...
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# CHECK-LABEL: Bad machine code: LiveVariables: Block should not be in AliveBlocks
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# CHECK-NEXT: - function: testfloatslt
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# CHECK-NEXT: - basic block: %bb.1 entry
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# CHECK-NEXT: Virtual register %4 is not needed live through the block.
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# CHECK-LABEL: Bad machine code: LiveVariables: Block should not be in AliveBlocks
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# CHECK-NEXT: - function: testfloatslt
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# CHECK-NEXT: - basic block: %bb.1 entry
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# CHECK-NEXT: Virtual register %5 is not needed live through the block.
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# CHECK-LABEL: Bad machine code: LiveVariables: Block should not be in AliveBlocks
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# CHECK-NEXT: - function: testfloatslt
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# CHECK-NEXT: - basic block: %bb.2 entry
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# CHECK-NEXT: Virtual register %5 is not needed live through the block.
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# CHECK-NEXT: LLVM ERROR: Found 3 machine code errors.
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