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DAG: Use Register

This commit is contained in:
Matt Arsenault 2020-04-08 12:26:32 -04:00 committed by Matt Arsenault
parent d0b57b41f4
commit 586769cce2
11 changed files with 109 additions and 108 deletions
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38
llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
View File

@ -67,7 +67,7 @@ public:
/// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
/// allocated to hold a pointer to the hidden sret parameter. /// allocated to hold a pointer to the hidden sret parameter.
unsigned DemoteRegister; Register DemoteRegister;
/// MBBMap - A mapping from LLVM basic blocks to their machine code entry. /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap; DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
@ -75,27 +75,27 @@ public:
/// ValueMap - Since we emit code for the function a basic block at a time, /// ValueMap - Since we emit code for the function a basic block at a time,
/// we must remember which virtual registers hold the values for /// we must remember which virtual registers hold the values for
/// cross-basic-block values. /// cross-basic-block values.
DenseMap<const Value *, unsigned> ValueMap; DenseMap<const Value *, Register> ValueMap;
/// VirtReg2Value map is needed by the Divergence Analysis driven /// VirtReg2Value map is needed by the Divergence Analysis driven
/// instruction selection. It is reverted ValueMap. It is computed /// instruction selection. It is reverted ValueMap. It is computed
/// in lazy style - on demand. It is used to get the Value corresponding /// in lazy style - on demand. It is used to get the Value corresponding
/// to the live in virtual register and is called from the /// to the live in virtual register and is called from the
/// TargetLowerinInfo::isSDNodeSourceOfDivergence. /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
DenseMap<unsigned, const Value*> VirtReg2Value; DenseMap<Register, const Value*> VirtReg2Value;
/// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
/// to get the Value corresponding to the live-in virtual register. /// to get the Value corresponding to the live-in virtual register.
const Value * getValueFromVirtualReg(unsigned Vreg); const Value *getValueFromVirtualReg(Register Vreg);
/// Track virtual registers created for exception pointers. /// Track virtual registers created for exception pointers.
DenseMap<const Value *, unsigned> CatchPadExceptionPointers; DenseMap<const Value *, Register> CatchPadExceptionPointers;
/// Keep track of frame indices allocated for statepoints as they could be /// Keep track of frame indices allocated for statepoints as they could be
/// used across basic block boundaries (e.g. for an invoke). For each /// used across basic block boundaries (e.g. for an invoke). For each
/// gc.statepoint instruction, maps uniqued llvm IR values to the slots they /// gc.statepoint instruction, maps uniqued llvm IR values to the slots they
/// were spilled in. If a value is mapped to None it means we visited the /// were spilled in. If a value is mapped to None it means we visited the
/// value but didn't spill it (because it was a constant, for instance). /// value but didn't spill it (because it was a constant, for instance).
using StatepointSpillMapTy = DenseMap<const Value *, Optional<int>>; using StatepointSpillMapTy = DenseMap<const Value *, Optional<int>>;
DenseMap<const Instruction *, StatepointSpillMapTy> StatepointSpillMaps; DenseMap<const Instruction *, StatepointSpillMapTy> StatepointSpillMaps;
@ -116,9 +116,9 @@ public:
BitVector DescribedArgs; BitVector DescribedArgs;
/// RegFixups - Registers which need to be replaced after isel is done. /// RegFixups - Registers which need to be replaced after isel is done.
DenseMap<unsigned, unsigned> RegFixups; DenseMap<Register, Register> RegFixups;
DenseSet<unsigned> RegsWithFixups; DenseSet<Register> RegsWithFixups;
/// StatepointStackSlots - A list of temporary stack slots (frame indices) /// StatepointStackSlots - A list of temporary stack slots (frame indices)
/// used to spill values at a statepoint. We store them here to enable /// used to spill values at a statepoint. We store them here to enable
@ -176,17 +176,17 @@ public:
return ValueMap.count(V); return ValueMap.count(V);
} }
unsigned CreateReg(MVT VT, bool isDivergent = false); Register CreateReg(MVT VT, bool isDivergent = false);
unsigned CreateRegs(const Value *V); Register CreateRegs(const Value *V);
unsigned CreateRegs(Type *Ty, bool isDivergent = false); Register CreateRegs(Type *Ty, bool isDivergent = false);
unsigned InitializeRegForValue(const Value *V) { Register InitializeRegForValue(const Value *V) {
// Tokens never live in vregs. // Tokens never live in vregs.
if (V->getType()->isTokenTy()) if (V->getType()->isTokenTy())
return 0; return 0;
unsigned &R = ValueMap[V]; Register &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!"); assert(R == 0 && "Already initialized this value register!");
assert(VirtReg2Value.empty()); assert(VirtReg2Value.empty());
return R = CreateRegs(V); return R = CreateRegs(V);
@ -194,7 +194,7 @@ public:
/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
/// register is a PHI destination and the PHI's LiveOutInfo is not valid. /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { const LiveOutInfo *GetLiveOutRegInfo(Register Reg) {
if (!LiveOutRegInfo.inBounds(Reg)) if (!LiveOutRegInfo.inBounds(Reg))
return nullptr; return nullptr;
@ -210,10 +210,10 @@ public:
/// the register's LiveOutInfo is for a smaller bit width, it is extended to /// the register's LiveOutInfo is for a smaller bit width, it is extended to
/// the larger bit width by zero extension. The bit width must be no smaller /// the larger bit width by zero extension. The bit width must be no smaller
/// than the LiveOutInfo's existing bit width. /// than the LiveOutInfo's existing bit width.
const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth); const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
/// AddLiveOutRegInfo - Adds LiveOutInfo for a register. /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
const KnownBits &Known) { const KnownBits &Known) {
// Only install this information if it tells us something. // Only install this information if it tells us something.
if (NumSignBits == 1 && Known.isUnknown()) if (NumSignBits == 1 && Known.isUnknown())
@ -234,11 +234,11 @@ public:
/// called when a block is visited before all of its predecessors. /// called when a block is visited before all of its predecessors.
void InvalidatePHILiveOutRegInfo(const PHINode *PN) { void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
// PHIs with no uses have no ValueMap entry. // PHIs with no uses have no ValueMap entry.
DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN); DenseMap<const Value*, Register>::const_iterator It = ValueMap.find(PN);
if (It == ValueMap.end()) if (It == ValueMap.end())
return; return;
unsigned Reg = It->second; Register Reg = It->second;
if (Reg == 0) if (Reg == 0)
return; return;
@ -253,7 +253,7 @@ public:
/// getArgumentFrameIndex - Get frame index for the byval argument. /// getArgumentFrameIndex - Get frame index for the byval argument.
int getArgumentFrameIndex(const Argument *A); int getArgumentFrameIndex(const Argument *A);
unsigned getCatchPadExceptionPointerVReg(const Value *CPI, Register getCatchPadExceptionPointerVReg(const Value *CPI,
const TargetRegisterClass *RC); const TargetRegisterClass *RC);
private: private:

7
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -30,6 +30,7 @@
#include "llvm/ADT/iterator_range.h" #include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Constants.h" #include "llvm/IR/Constants.h"
#include "llvm/IR/DebugLoc.h" #include "llvm/IR/DebugLoc.h"
@ -2034,13 +2035,13 @@ public:
class RegisterSDNode : public SDNode { class RegisterSDNode : public SDNode {
friend class SelectionDAG; friend class SelectionDAG;
unsigned Reg; Register Reg;
RegisterSDNode(unsigned reg, EVT VT) RegisterSDNode(Register reg, EVT VT)
: SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {} : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
public: public:
unsigned getReg() const { return Reg; } Register getReg() const { return Reg; }
static bool classof(const SDNode *N) { static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::Register; return N->getOpcode() == ISD::Register;

8
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -492,7 +492,7 @@ Register FastISel::lookUpRegForValue(const Value *V) {
// cache values defined by Instructions across blocks, and other values // cache values defined by Instructions across blocks, and other values
// only locally. This is because Instructions already have the SSA // only locally. This is because Instructions already have the SSA
// def-dominates-use requirement enforced. // def-dominates-use requirement enforced.
DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(V);
if (I != FuncInfo.ValueMap.end()) if (I != FuncInfo.ValueMap.end())
return I->second; return I->second;
return LocalValueMap[V]; return LocalValueMap[V];
@ -504,8 +504,8 @@ void FastISel::updateValueMap(const Value *I, Register Reg, unsigned NumRegs) {
return; return;
} }
unsigned &AssignedReg = FuncInfo.ValueMap[I]; Register &AssignedReg = FuncInfo.ValueMap[I];
if (AssignedReg == 0) if (!AssignedReg)
// Use the new register. // Use the new register.
AssignedReg = Reg; AssignedReg = Reg;
else if (Reg != AssignedReg) { else if (Reg != AssignedReg) {
@ -1807,7 +1807,7 @@ bool FastISel::selectExtractValue(const User *U) {
// Get the base result register. // Get the base result register.
unsigned ResultReg; unsigned ResultReg;
DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0); DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
if (I != FuncInfo.ValueMap.end()) if (I != FuncInfo.ValueMap.end())
ResultReg = I->second; ResultReg = I->second;
else if (isa<Instruction>(Op0)) else if (isa<Instruction>(Op0))

26
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -352,7 +352,7 @@ void FunctionLoweringInfo::clear() {
} }
/// CreateReg - Allocate a single virtual register for the given type. /// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
return RegInfo->createVirtualRegister( return RegInfo->createVirtualRegister(
MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent)); MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
} }
@ -364,27 +364,27 @@ unsigned FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
/// In the case that the given value has struct or array type, this function /// In the case that the given value has struct or array type, this function
/// will assign registers for each member or element. /// will assign registers for each member or element.
/// ///
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
const TargetLowering *TLI = MF->getSubtarget().getTargetLowering(); const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
SmallVector<EVT, 4> ValueVTs; SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs); ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
unsigned FirstReg = 0; Register FirstReg;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {
unsigned R = CreateReg(RegisterVT, isDivergent); Register R = CreateReg(RegisterVT, isDivergent);
if (!FirstReg) FirstReg = R; if (!FirstReg) FirstReg = R;
} }
} }
return FirstReg; return FirstReg;
} }
unsigned FunctionLoweringInfo::CreateRegs(const Value *V) { Register FunctionLoweringInfo::CreateRegs(const Value *V) {
return CreateRegs(V->getType(), DA && DA->isDivergent(V) && return CreateRegs(V->getType(), DA && DA->isDivergent(V) &&
!TLI->requiresUniformRegister(*MF, V)); !TLI->requiresUniformRegister(*MF, V));
} }
@ -395,7 +395,7 @@ unsigned FunctionLoweringInfo::CreateRegs(const Value *V) {
/// the larger bit width by zero extension. The bit width must be no smaller /// the larger bit width by zero extension. The bit width must be no smaller
/// than the LiveOutInfo's existing bit width. /// than the LiveOutInfo's existing bit width.
const FunctionLoweringInfo::LiveOutInfo * const FunctionLoweringInfo::LiveOutInfo *
FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) { FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
if (!LiveOutRegInfo.inBounds(Reg)) if (!LiveOutRegInfo.inBounds(Reg))
return nullptr; return nullptr;
@ -429,7 +429,7 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
unsigned BitWidth = IntVT.getSizeInBits(); unsigned BitWidth = IntVT.getSizeInBits();
unsigned DestReg = ValueMap[PN]; Register DestReg = ValueMap[PN];
if (!Register::isVirtualRegister(DestReg)) if (!Register::isVirtualRegister(DestReg))
return; return;
LiveOutRegInfo.grow(DestReg); LiveOutRegInfo.grow(DestReg);
@ -450,7 +450,7 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
} else { } else {
assert(ValueMap.count(V) && "V should have been placed in ValueMap when its" assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
"CopyToReg node was created."); "CopyToReg node was created.");
unsigned SrcReg = ValueMap[V]; Register SrcReg = ValueMap[V];
if (!Register::isVirtualRegister(SrcReg)) { if (!Register::isVirtualRegister(SrcReg)) {
DestLOI.IsValid = false; DestLOI.IsValid = false;
return; return;
@ -485,8 +485,8 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
assert(ValueMap.count(V) && "V should have been placed in ValueMap when " assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
"its CopyToReg node was created."); "its CopyToReg node was created.");
unsigned SrcReg = ValueMap[V]; Register SrcReg = ValueMap[V];
if (!Register::isVirtualRegister(SrcReg)) { if (!SrcReg.isVirtual()) {
DestLOI.IsValid = false; DestLOI.IsValid = false;
return; return;
} }
@ -520,11 +520,11 @@ int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
return INT_MAX; return INT_MAX;
} }
unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg( Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
const Value *CPI, const TargetRegisterClass *RC) { const Value *CPI, const TargetRegisterClass *RC) {
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
auto I = CatchPadExceptionPointers.insert({CPI, 0}); auto I = CatchPadExceptionPointers.insert({CPI, 0});
unsigned &VReg = I.first->second; Register &VReg = I.first->second;
if (I.second) if (I.second)
VReg = MRI.createVirtualRegister(RC); VReg = MRI.createVirtualRegister(RC);
assert(VReg && "null vreg in exception pointer table!"); assert(VReg && "null vreg in exception pointer table!");
@ -532,7 +532,7 @@ unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
} }
const Value * const Value *
FunctionLoweringInfo::getValueFromVirtualReg(unsigned Vreg) { FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
if (VirtReg2Value.empty()) { if (VirtReg2Value.empty()) {
SmallVector<EVT, 4> ValueVTs; SmallVector<EVT, 4> ValueVTs;
for (auto &P : ValueMap) { for (auto &P : ValueMap) {

54
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -84,9 +84,9 @@ static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
/// implicit physical register output. /// implicit physical register output.
void InstrEmitter:: void InstrEmitter::
EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap) {
unsigned VRBase = 0; Register VRBase;
if (Register::isVirtualRegister(SrcReg)) { if (SrcReg.isVirtual()) {
// Just use the input register directly! // Just use the input register directly!
SDValue Op(Node, ResNo); SDValue Op(Node, ResNo);
if (IsClone) if (IsClone)
@ -113,8 +113,8 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
if (User->getOpcode() == ISD::CopyToReg && if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).getNode() == Node && User->getOperand(2).getNode() == Node &&
User->getOperand(2).getResNo() == ResNo) { User->getOperand(2).getResNo() == ResNo) {
unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (Register::isVirtualRegister(DestReg)) { if (DestReg.isVirtual()) {
VRBase = DestReg; VRBase = DestReg;
Match = false; Match = false;
} else if (DestReg != SrcReg) } else if (DestReg != SrcReg)
@ -190,7 +190,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
MachineInstrBuilder &MIB, MachineInstrBuilder &MIB,
const MCInstrDesc &II, const MCInstrDesc &II,
bool IsClone, bool IsCloned, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"); "IMPLICIT_DEF should have been handled as a special case elsewhere!");
@ -202,7 +202,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
// If the specific node value is only used by a CopyToReg and the dest reg // If the specific node value is only used by a CopyToReg and the dest reg
// is a vreg in the same register class, use the CopyToReg'd destination // is a vreg in the same register class, use the CopyToReg'd destination
// register instead of creating a new vreg. // register instead of creating a new vreg.
unsigned VRBase = 0; Register VRBase;
const TargetRegisterClass *RC = const TargetRegisterClass *RC =
TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
// Always let the value type influence the used register class. The // Always let the value type influence the used register class. The
@ -222,7 +222,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) { if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
// Optional def must be a physical register. // Optional def must be a physical register.
VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
assert(Register::isPhysicalRegister(VRBase)); assert(VRBase.isPhysical());
MIB.addReg(VRBase, RegState::Define); MIB.addReg(VRBase, RegState::Define);
} }
@ -266,8 +266,8 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
/// getVR - Return the virtual register corresponding to the specified result /// getVR - Return the virtual register corresponding to the specified result
/// of the specified node. /// of the specified node.
unsigned InstrEmitter::getVR(SDValue Op, Register InstrEmitter::getVR(SDValue Op,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
if (Op.isMachineOpcode() && if (Op.isMachineOpcode() &&
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use. // Add an IMPLICIT_DEF instruction before every use.
@ -281,7 +281,7 @@ unsigned InstrEmitter::getVR(SDValue Op,
return VReg; return VReg;
} }
DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late"); assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second; return I->second;
} }
@ -295,13 +295,13 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
SDValue Op, SDValue Op,
unsigned IIOpNum, unsigned IIOpNum,
const MCInstrDesc *II, const MCInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
bool IsDebug, bool IsClone, bool IsCloned) { bool IsDebug, bool IsClone, bool IsCloned) {
assert(Op.getValueType() != MVT::Other && assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Glue && Op.getValueType() != MVT::Glue &&
"Chain and glue operands should occur at end of operand list!"); "Chain and glue operands should occur at end of operand list!");
// Get/emit the operand. // Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap); Register VReg = getVR(Op, VRBaseMap);
const MCInstrDesc &MCID = MIB->getDesc(); const MCInstrDesc &MCID = MIB->getDesc();
bool isOptDef = IIOpNum < MCID.getNumOperands() && bool isOptDef = IIOpNum < MCID.getNumOperands() &&
@ -366,7 +366,7 @@ void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
SDValue Op, SDValue Op,
unsigned IIOpNum, unsigned IIOpNum,
const MCInstrDesc *II, const MCInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
bool IsDebug, bool IsClone, bool IsCloned) { bool IsDebug, bool IsClone, bool IsCloned) {
if (Op.isMachineOpcode()) { if (Op.isMachineOpcode()) {
AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
@ -376,7 +376,7 @@ void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
MIB.addFPImm(F->getConstantFPValue()); MIB.addFPImm(F->getConstantFPValue());
} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
unsigned VReg = R->getReg(); Register VReg = R->getReg();
MVT OpVT = Op.getSimpleValueType(); MVT OpVT = Op.getSimpleValueType();
const TargetRegisterClass *IIRC = const TargetRegisterClass *IIRC =
II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF)) II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
@ -449,7 +449,7 @@ void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
} }
} }
unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
MVT VT, bool isDivergent, const DebugLoc &DL) { MVT VT, bool isDivergent, const DebugLoc &DL) {
const TargetRegisterClass *VRC = MRI->getRegClass(VReg); const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
@ -476,9 +476,9 @@ unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/// EmitSubregNode - Generate machine code for subreg nodes. /// EmitSubregNode - Generate machine code for subreg nodes.
/// ///
void InstrEmitter::EmitSubregNode(SDNode *Node, void InstrEmitter::EmitSubregNode(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
bool IsClone, bool IsCloned) { bool IsClone, bool IsCloned) {
unsigned VRBase = 0; Register VRBase;
unsigned Opc = Node->getMachineOpcode(); unsigned Opc = Node->getMachineOpcode();
// If the node is only used by a CopyToReg and the dest reg is a vreg, use // If the node is only used by a CopyToReg and the dest reg is a vreg, use
@ -537,7 +537,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
Node->getOperand(0).getSimpleValueType(), Node->getOperand(0).getSimpleValueType(),
Node->isDivergent(), Node->getDebugLoc()); Node->isDivergent(), Node->getDebugLoc());
// Create the destreg if it is missing. // Create the destreg if it is missing.
if (VRBase == 0) if (!VRBase)
VRBase = MRI->createVirtualRegister(TRC); VRBase = MRI->createVirtualRegister(TRC);
// Create the extract_subreg machine instruction. // Create the extract_subreg machine instruction.
@ -610,7 +610,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
/// ///
void void
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
// Create the new VReg in the destination class and emit a copy. // Create the new VReg in the destination class and emit a copy.
@ -630,7 +630,7 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
/// ///
void InstrEmitter::EmitRegSequence(SDNode *Node, void InstrEmitter::EmitRegSequence(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
bool IsClone, bool IsCloned) { bool IsClone, bool IsCloned) {
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
@ -679,7 +679,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
/// ///
MachineInstr * MachineInstr *
InstrEmitter::EmitDbgValue(SDDbgValue *SD, InstrEmitter::EmitDbgValue(SDDbgValue *SD,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
MDNode *Var = SD->getVariable(); MDNode *Var = SD->getVariable();
MDNode *Expr = SD->getExpression(); MDNode *Expr = SD->getExpression();
DebugLoc DL = SD->getDebugLoc(); DebugLoc DL = SD->getDebugLoc();
@ -724,7 +724,7 @@ InstrEmitter::EmitDbgValue(SDDbgValue *SD,
// they happen and transfer the debug info, but trying to guarantee that // they happen and transfer the debug info, but trying to guarantee that
// in all cases would be very fragile; this is a safeguard for any // in all cases would be very fragile; this is a safeguard for any
// that were missed. // that were missed.
DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
if (I==VRBaseMap.end()) if (I==VRBaseMap.end())
MIB.addReg(0U); // undef MIB.addReg(0U); // undef
else else
@ -785,7 +785,7 @@ InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
/// ///
void InstrEmitter:: void InstrEmitter::
EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
unsigned Opc = Node->getMachineOpcode(); unsigned Opc = Node->getMachineOpcode();
// Handle subreg insert/extract specially // Handle subreg insert/extract specially
@ -986,7 +986,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
/// needed dependencies. /// needed dependencies.
void InstrEmitter:: void InstrEmitter::
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
switch (Node->getOpcode()) { switch (Node->getOpcode()) {
default: default:
#ifndef NDEBUG #ifndef NDEBUG
@ -999,7 +999,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
case ISD::TokenFactor: // fall thru case ISD::TokenFactor: // fall thru
break; break;
case ISD::CopyToReg: { case ISD::CopyToReg: {
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
SDValue SrcVal = Node->getOperand(2); SDValue SrcVal = Node->getOperand(2);
if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() && if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
@ -1009,7 +1009,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
break; break;
} }
unsigned SrcReg; Register SrcReg;
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
SrcReg = R->getReg(); SrcReg = R->getReg();
else else

30
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h
View File

@ -39,19 +39,19 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
/// implicit physical register output. /// implicit physical register output.
void EmitCopyFromReg(SDNode *Node, unsigned ResNo, void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
bool IsClone, bool IsCloned, bool IsClone, bool IsCloned,
unsigned SrcReg, Register SrcReg,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, void CreateVirtualRegisters(SDNode *Node,
MachineInstrBuilder &MIB, MachineInstrBuilder &MIB,
const MCInstrDesc &II, const MCInstrDesc &II,
bool IsClone, bool IsCloned, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
/// getVR - Return the virtual register corresponding to the specified result /// getVR - Return the virtual register corresponding to the specified result
/// of the specified node. /// of the specified node.
unsigned getVR(SDValue Op, Register getVR(SDValue Op,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
/// AddRegisterOperand - Add the specified register as an operand to the /// AddRegisterOperand - Add the specified register as an operand to the
/// specified machine instr. Insert register copies if the register is /// specified machine instr. Insert register copies if the register is
@ -60,7 +60,7 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
SDValue Op, SDValue Op,
unsigned IIOpNum, unsigned IIOpNum,
const MCInstrDesc *II, const MCInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
bool IsDebug, bool IsClone, bool IsCloned); bool IsDebug, bool IsClone, bool IsCloned);
/// AddOperand - Add the specified operand to the specified machine instr. II /// AddOperand - Add the specified operand to the specified machine instr. II
@ -71,18 +71,18 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
SDValue Op, SDValue Op,
unsigned IIOpNum, unsigned IIOpNum,
const MCInstrDesc *II, const MCInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
bool IsDebug, bool IsClone, bool IsCloned); bool IsDebug, bool IsClone, bool IsCloned);
/// ConstrainForSubReg - Try to constrain VReg to a register class that /// ConstrainForSubReg - Try to constrain VReg to a register class that
/// supports SubIdx sub-registers. Emit a copy if that isn't possible. /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
/// Return the virtual register to use. /// Return the virtual register to use.
unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, MVT VT, Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
bool isDivergent, const DebugLoc &DL); bool isDivergent, const DebugLoc &DL);
/// EmitSubregNode - Generate machine code for subreg nodes. /// EmitSubregNode - Generate machine code for subreg nodes.
/// ///
void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
bool IsClone, bool IsCloned); bool IsClone, bool IsCloned);
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
@ -90,11 +90,11 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter {
/// register is constrained to be in a particular register class. /// register is constrained to be in a particular register class.
/// ///
void EmitCopyToRegClassNode(SDNode *Node, void EmitCopyToRegClassNode(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
/// ///
void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
bool IsClone, bool IsCloned); bool IsClone, bool IsCloned);
public: public:
/// CountResults - The results of target nodes have register or immediate /// CountResults - The results of target nodes have register or immediate
@ -105,7 +105,7 @@ public:
/// EmitDbgValue - Generate machine instruction for a dbg_value node. /// EmitDbgValue - Generate machine instruction for a dbg_value node.
/// ///
MachineInstr *EmitDbgValue(SDDbgValue *SD, MachineInstr *EmitDbgValue(SDDbgValue *SD,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
/// Generate machine instruction for a dbg_label node. /// Generate machine instruction for a dbg_label node.
MachineInstr *EmitDbgLabel(SDDbgLabel *SD); MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
@ -113,7 +113,7 @@ public:
/// EmitNode - Generate machine code for a node and needed dependencies. /// EmitNode - Generate machine code for a node and needed dependencies.
/// ///
void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap) { DenseMap<SDValue, Register> &VRBaseMap) {
if (Node->isMachineOpcode()) if (Node->isMachineOpcode())
EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
else else
@ -132,9 +132,9 @@ public:
private: private:
void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap); DenseMap<SDValue, Register> &VRBaseMap);
}; };
} }

2
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -761,7 +761,7 @@ void ScheduleDAGLinearize::Schedule() {
MachineBasicBlock* MachineBasicBlock*
ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) { ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
InstrEmitter Emitter(BB, InsertPos); InstrEmitter Emitter(BB, InsertPos);
DenseMap<SDValue, unsigned> VRBaseMap; DenseMap<SDValue, Register> VRBaseMap;
LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; }); LLVM_DEBUG({ dbgs() << "\n*** Final schedule ***\n"; });

20
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -734,7 +734,7 @@ void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
static void static void
ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) { DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) {
if (!N->getHasDebugValue()) if (!N->getHasDebugValue())
return; return;
@ -761,9 +761,9 @@ ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
// instructions in the right order. // instructions in the right order.
static void static void
ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
DenseMap<SDValue, unsigned> &VRBaseMap, DenseMap<SDValue, Register> &VRBaseMap,
SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders, SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders,
SmallSet<unsigned, 8> &Seen, MachineInstr *NewInsn) { SmallSet<Register, 8> &Seen, MachineInstr *NewInsn) {
unsigned Order = N->getIROrder(); unsigned Order = N->getIROrder();
if (!Order || Seen.count(Order)) { if (!Order || Seen.count(Order)) {
// Process any valid SDDbgValues even if node does not have any order // Process any valid SDDbgValues even if node does not have any order
@ -787,17 +787,17 @@ ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
} }
void ScheduleDAGSDNodes:: void ScheduleDAGSDNodes::
EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap, EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
MachineBasicBlock::iterator InsertPos) { MachineBasicBlock::iterator InsertPos) {
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) { I != E; ++I) {
if (I->isCtrl()) continue; // ignore chain preds if (I->isCtrl()) continue; // ignore chain preds
if (I->getSUnit()->CopyDstRC) { if (I->getSUnit()->CopyDstRC) {
// Copy to physical register. // Copy to physical register.
DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit()); DenseMap<SUnit*, Register>::iterator VRI = VRBaseMap.find(I->getSUnit());
assert(VRI != VRBaseMap.end() && "Node emitted out of order - late"); assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
// Find the destination physical register. // Find the destination physical register.
unsigned Reg = 0; Register Reg;
for (SUnit::const_succ_iterator II = SU->Succs.begin(), for (SUnit::const_succ_iterator II = SU->Succs.begin(),
EE = SU->Succs.end(); II != EE; ++II) { EE = SU->Succs.end(); II != EE; ++II) {
if (II->isCtrl()) continue; // ignore chain preds if (II->isCtrl()) continue; // ignore chain preds
@ -829,17 +829,17 @@ EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
MachineBasicBlock *ScheduleDAGSDNodes:: MachineBasicBlock *ScheduleDAGSDNodes::
EmitSchedule(MachineBasicBlock::iterator &InsertPos) { EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
InstrEmitter Emitter(BB, InsertPos); InstrEmitter Emitter(BB, InsertPos);
DenseMap<SDValue, unsigned> VRBaseMap; DenseMap<SDValue, Register> VRBaseMap;
DenseMap<SUnit*, unsigned> CopyVRBaseMap; DenseMap<SUnit*, Register> CopyVRBaseMap;
SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
SmallSet<unsigned, 8> Seen; SmallSet<Register, 8> Seen;
bool HasDbg = DAG->hasDebugValues(); bool HasDbg = DAG->hasDebugValues();
// Emit a node, and determine where its first instruction is for debuginfo. // Emit a node, and determine where its first instruction is for debuginfo.
// Zero, one, or multiple instructions can be created when emitting a node. // Zero, one, or multiple instructions can be created when emitting a node.
auto EmitNode = auto EmitNode =
[&](SDNode *Node, bool IsClone, bool IsCloned, [&](SDNode *Node, bool IsClone, bool IsCloned,
DenseMap<SDValue, unsigned> &VRBaseMap) -> MachineInstr * { DenseMap<SDValue, Register> &VRBaseMap) -> MachineInstr * {
// Fetch instruction prior to this, or end() if nonexistant. // Fetch instruction prior to this, or end() if nonexistant.
auto GetPrevInsn = [&](MachineBasicBlock::iterator I) { auto GetPrevInsn = [&](MachineBasicBlock::iterator I) {
if (I == BB->begin()) if (I == BB->begin())

2
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
View File

@ -184,7 +184,7 @@ class InstrItineraryData;
void BuildSchedUnits(); void BuildSchedUnits();
void AddSchedEdges(); void AddSchedEdges();
void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap, void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap,
MachineBasicBlock::iterator InsertPos); MachineBasicBlock::iterator InsertPos);
}; };

12
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -1397,11 +1397,11 @@ void SelectionDAGBuilder::resolveOrClearDbgInfo() {
/// getCopyFromRegs - If there was virtual register allocated for the value V /// getCopyFromRegs - If there was virtual register allocated for the value V
/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise. /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) { SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); DenseMap<const Value *, Register>::iterator It = FuncInfo.ValueMap.find(V);
SDValue Result; SDValue Result;
if (It != FuncInfo.ValueMap.end()) { if (It != FuncInfo.ValueMap.end()) {
unsigned InReg = It->second; Register InReg = It->second;
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
DAG.getDataLayout(), InReg, Ty, DAG.getDataLayout(), InReg, Ty,
@ -1963,7 +1963,7 @@ void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
if (V->getType()->isEmptyTy()) if (V->getType()->isEmptyTy())
return; return;
DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); DenseMap<const Value *, Register>::iterator VMI = FuncInfo.ValueMap.find(V);
if (VMI != FuncInfo.ValueMap.end()) { if (VMI != FuncInfo.ValueMap.end()) {
assert(!V->use_empty() && "Unused value assigned virtual registers!"); assert(!V->use_empty() && "Unused value assigned virtual registers!");
CopyValueToVirtualRegister(V, VMI->second); CopyValueToVirtualRegister(V, VMI->second);
@ -4601,7 +4601,7 @@ void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
PendingLoads.push_back(OutChain); PendingLoads.push_back(OutChain);
return; return;
} }
SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain, SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
Ptr, MMO); Ptr, MMO);
@ -5534,7 +5534,7 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
}; };
// Check if ValueMap has reg number. // Check if ValueMap has reg number.
DenseMap<const Value *, unsigned>::const_iterator DenseMap<const Value *, Register>::const_iterator
VMI = FuncInfo.ValueMap.find(V); VMI = FuncInfo.ValueMap.find(V);
if (VMI != FuncInfo.ValueMap.end()) { if (VMI != FuncInfo.ValueMap.end()) {
const auto &TLI = DAG.getTargetLoweringInfo(); const auto &TLI = DAG.getTargetLoweringInfo();
@ -9933,7 +9933,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
} }
Reg = RegOut; Reg = RegOut;
} else { } else {
DenseMap<const Value *, unsigned>::iterator I = DenseMap<const Value *, Register>::iterator I =
FuncInfo.ValueMap.find(PHIOp); FuncInfo.ValueMap.find(PHIOp);
if (I != FuncInfo.ValueMap.end()) if (I != FuncInfo.ValueMap.end())
Reg = I->second; Reg = I->second;

18
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -513,15 +513,15 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// registers. If we don't apply the reg fixups before, some registers may // registers. If we don't apply the reg fixups before, some registers may
// appear as unused and will be skipped, resulting in bad MI. // appear as unused and will be skipped, resulting in bad MI.
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
for (DenseMap<unsigned, unsigned>::iterator I = FuncInfo->RegFixups.begin(), for (DenseMap<Register, Register>::iterator I = FuncInfo->RegFixups.begin(),
E = FuncInfo->RegFixups.end(); E = FuncInfo->RegFixups.end();
I != E; ++I) { I != E; ++I) {
unsigned From = I->first; Register From = I->first;
unsigned To = I->second; Register To = I->second;
// If To is also scheduled to be replaced, find what its ultimate // If To is also scheduled to be replaced, find what its ultimate
// replacement is. // replacement is.
while (true) { while (true) {
DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); DenseMap<Register, Register>::iterator J = FuncInfo->RegFixups.find(To);
if (J == E) if (J == E)
break; break;
To = J->second; To = J->second;
@ -660,15 +660,15 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// Replace forward-declared registers with the registers containing // Replace forward-declared registers with the registers containing
// the desired value. // the desired value.
for (DenseMap<unsigned, unsigned>::iterator for (DenseMap<Register, Register>::iterator
I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
I != E; ++I) { I != E; ++I) {
unsigned From = I->first; Register From = I->first;
unsigned To = I->second; Register To = I->second;
// If To is also scheduled to be replaced, find what its ultimate // If To is also scheduled to be replaced, find what its ultimate
// replacement is. // replacement is.
while (true) { while (true) {
DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); DenseMap<Register, Register>::iterator J = FuncInfo->RegFixups.find(To);
if (J == E) break; if (J == E) break;
To = J->second; To = J->second;
} }
@ -1537,7 +1537,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() && if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
!Inst->use_empty()) { !Inst->use_empty()) {
unsigned &R = FuncInfo->ValueMap[Inst]; Register &R = FuncInfo->ValueMap[Inst];
if (!R) if (!R)
R = FuncInfo->CreateRegs(Inst); R = FuncInfo->CreateRegs(Inst);
} }