forked from OSchip/llvm-project
[RISCV] Remove FCSR from RISCVRegisterInfo.
We only used this to mark it as a reserved register. But that's not important if we don't do anything else with it. I think if we were ever to do anything with it, we would need to model it as a super register of FRM and FFLAGS. But it might be easier to reference both FRM and FFLAGS in implicit defs/uses for anything we were to do with "fcsr". Reviewed By: sepavloff Differential Revision: https://reviews.llvm.org/D115455
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@ -105,7 +105,6 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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// Floating point environment registers.
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// Floating point environment registers.
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markSuperRegs(Reserved, RISCV::FRM);
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markSuperRegs(Reserved, RISCV::FRM);
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markSuperRegs(Reserved, RISCV::FFLAGS);
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markSuperRegs(Reserved, RISCV::FFLAGS);
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markSuperRegs(Reserved, RISCV::FCSR);
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assert(checkAllSuperRegsMarked(Reserved));
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assert(checkAllSuperRegsMarked(Reserved));
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return Reserved;
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return Reserved;
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@ -577,7 +577,6 @@ foreach m = LMULList.m in {
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// Special registers
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// Special registers
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def FFLAGS : RISCVReg<0, "fflags">;
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def FFLAGS : RISCVReg<0, "fflags">;
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def FRM : RISCVReg<0, "frm">;
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def FRM : RISCVReg<0, "frm">;
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def FCSR : RISCVReg<0, "fcsr">;
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// Any type register. Used for .insn directives when we don't know what the
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// Any type register. Used for .insn directives when we don't know what the
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// register types could be.
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// register types could be.
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