forked from OSchip/llvm-project
[RISCV] Remove FCSR from RISCVRegisterInfo.
We only used this to mark it as a reserved register. But that's not important if we don't do anything else with it. I think if we were ever to do anything with it, we would need to model it as a super register of FRM and FFLAGS. But it might be easier to reference both FRM and FFLAGS in implicit defs/uses for anything we were to do with "fcsr". Reviewed By: sepavloff Differential Revision: https://reviews.llvm.org/D115455
This commit is contained in:
parent
57b5f4b2ec
commit
5861cf77da
|
@ -105,7 +105,6 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
// Floating point environment registers.
|
||||
markSuperRegs(Reserved, RISCV::FRM);
|
||||
markSuperRegs(Reserved, RISCV::FFLAGS);
|
||||
markSuperRegs(Reserved, RISCV::FCSR);
|
||||
|
||||
assert(checkAllSuperRegsMarked(Reserved));
|
||||
return Reserved;
|
||||
|
|
|
@ -577,7 +577,6 @@ foreach m = LMULList.m in {
|
|||
// Special registers
|
||||
def FFLAGS : RISCVReg<0, "fflags">;
|
||||
def FRM : RISCVReg<0, "frm">;
|
||||
def FCSR : RISCVReg<0, "fcsr">;
|
||||
|
||||
// Any type register. Used for .insn directives when we don't know what the
|
||||
// register types could be.
|
||||
|
|
Loading…
Reference in New Issue