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ARM parsing and encoding for LDRB instruction. 

llvm-svn: 137071
This commit is contained in:
Jim Grosbach 2011-08-08 22:37:06 +00:00
parent f6dbc3a57c
commit 5838c0c47e
1 changed files with 38 additions and 0 deletions
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38
llvm/test/MC/ARM/arm-memory-instructions.s
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@ -51,3 +51,41 @@ _func:
@ CHECK: ldr r4, [r3], -r6 @ encoding: [0x06,0x40,0x13,0xe6]
@ CHECK: ldr r3, [r8, -r2, lsl #15] @ encoding: [0x82,0x37,0x18,0xe7]
@ CHECK: ldr r1, [r5], r3, asr #15 @ encoding: [0xc3,0x17,0x95,0xe6]
@------------------------------------------------------------------------------
@ LDRB (immediate)
@------------------------------------------------------------------------------
ldrb r3, [r8]
ldrb r1, [sp, #63]
ldrb r9, [r3, #4095]!
ldrb r8, [r1], #22
ldrb r2, [r7], #-19
@ CHECK: ldrb r3, [r8] @ encoding: [0x00,0x30,0xd8,0xe5]
@ CHECK: ldrb r1, [sp, #63] @ encoding: [0x3f,0x10,0xdd,0xe5]
@ CHECK: ldrb r9, [r3, #4095]! @ encoding: [0xff,0x9f,0xf3,0xe5]
@ CHECK: ldrb r8, [r1], #22 @ encoding: [0x16,0x80,0xd1,0xe4]
@ CHECK: ldrb r2, [r7], #-19 @ encoding: [0x13,0x20,0x57,0xe4]
@------------------------------------------------------------------------------
@ LDRB (register)
@------------------------------------------------------------------------------
ldr r9, [r8, r5]
ldr r1, [r5, -r1]
ldr r3, [r5, r2]!
ldr r6, [r9, -r3]!
ldr r2, [r1], r4
ldr r8, [r4], -r5
ldr r7, [r12, -r1, lsl #15]
ldr r5, [r2], r9, asr #15
@ CHECK: ldr r9, [r8, r5] @ encoding: [0x05,0x90,0x98,0xe7]
@ CHECK: ldr r1, [r5, -r1] @ encoding: [0x01,0x10,0x15,0xe7]
@ CHECK: ldr r3, [r5, r2]! @ encoding: [0x02,0x30,0xb5,0xe7]
@ CHECK: ldr r6, [r9, -r3]! @ encoding: [0x03,0x60,0x39,0xe7]
@ CHECK: ldr r2, [r1], r4 @ encoding: [0x04,0x20,0x91,0xe6]
@ CHECK: ldr r8, [r4], -r5 @ encoding: [0x05,0x80,0x14,0xe6]
@ CHECK: ldr r7, [r12, -r1, lsl #15] @ encoding: [0x81,0x77,0x1c,0xe7]
@ CHECK: ldr r5, [r2], r9, asr #15 @ encoding: [0xc9,0x57,0x92,0xe6]