forked from OSchip/llvm-project
parent
9696f63d3e
commit
5815a6e455
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@ -133,6 +133,10 @@ def SDTBr : SDTypeProfile<0, 1, [ // br
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def SDTRet : SDTypeProfile<0, 0, []>; // ret
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def SDTReadPort : SDTypeProfile<1, 1, [ // readport
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SDTCisInt<0>, SDTCisInt<1>
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]>;
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def SDTWritePort : SDTypeProfile<0, 2, [ // writeport
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SDTCisInt<0>, SDTCisInt<1>
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]>;
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@ -254,6 +258,7 @@ def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
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def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
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def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
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def readport : SDNode<"ISD::READPORT" , SDTReadPort, [SDNPHasChain]>;
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def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
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def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
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@ -399,18 +399,27 @@ def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>,
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// Input/Output Instructions...
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//
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def IN8rr : I<0xEC, RawFrm, (ops),
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"in{b} {%dx, %al|%AL, %DX}", []>, Imp<[DX], [AL]>;
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"in{b} {%dx, %al|%AL, %DX}",
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[(set AL, (readport DX))]>, Imp<[DX], [AL]>;
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def IN16rr : I<0xED, RawFrm, (ops),
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"in{w} {%dx, %ax|%AX, %DX}", []>, Imp<[DX], [AX]>, OpSize;
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"in{w} {%dx, %ax|%AX, %DX}",
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[(set AX, (readport DX))]>, Imp<[DX], [AX]>, OpSize;
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def IN32rr : I<0xED, RawFrm, (ops),
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"in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
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"in{l} {%dx, %eax|%EAX, %DX}",
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[(set EAX, (readport DX))]>, Imp<[DX],[EAX]>;
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def IN8ri : Ii8<0xE4, RawFrm, (ops i8imm:$port),
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"in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>;
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def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
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"in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize;
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def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
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"in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
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def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
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"in{b} {$port, %al|%AL, $port}",
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[(set AL, (readport i16immZExt8:$port))]>,
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Imp<[], [AL]>;
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def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
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"in{w} {$port, %ax|%AX, $port}",
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[(set AX, (readport i16immZExt8:$port))]>,
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Imp<[], [AX]>, OpSize;
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def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
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"in{l} {$port, %eax|%EAX, $port}",
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[(set EAX, (readport i16immZExt8:$port))]>,
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Imp<[],[EAX]>;
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def OUT8rr : I<0xEE, RawFrm, (ops),
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"out{b} {%al, %dx|%DX, %AL}",
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