forked from OSchip/llvm-project
[X86][SSE] Add missing scheduling latency/throughput test for PINSRW
llvm-svn: 301136
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@ -3545,6 +3545,52 @@ define i16 @test_pextrw(<8 x i16> %a0) {
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ret i16 %1
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}
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define <8 x i16> @test_pinsrw(<8 x i16> %a0, i16 %a1, i16 *%a2) {
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; GENERIC-LABEL: test_pinsrw:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pinsrw $1, %edi, %xmm0
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; GENERIC-NEXT: pinsrw $3, (%rsi), %xmm0
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; GENERIC-NEXT: retq
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;
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; ATOM-LABEL: test_pinsrw:
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; ATOM: # BB#0:
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; ATOM-NEXT: pinsrw $1, %edi, %xmm0
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; ATOM-NEXT: pinsrw $3, (%rsi), %xmm0
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; ATOM-NEXT: nop
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; ATOM-NEXT: nop
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; ATOM-NEXT: nop
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; ATOM-NEXT: nop
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; ATOM-NEXT: retq
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;
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; SLM-LABEL: test_pinsrw:
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; SLM: # BB#0:
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; SLM-NEXT: pinsrw $1, %edi, %xmm0 # sched: [1:1.00]
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; SLM-NEXT: pinsrw $3, (%rsi), %xmm0 # sched: [4:1.00]
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; SLM-NEXT: retq # sched: [4:1.00]
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;
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; SANDY-LABEL: test_pinsrw:
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; SANDY: # BB#0:
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; SANDY-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.50]
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; SANDY-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [5:0.50]
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; SANDY-NEXT: retq # sched: [5:1.00]
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;
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; HASWELL-LABEL: test_pinsrw:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:1.00]
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; HASWELL-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [5:1.00]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; BTVER2-LABEL: test_pinsrw:
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; BTVER2: # BB#0:
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; BTVER2-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0 # sched: [1:0.50]
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; BTVER2-NEXT: vpinsrw $3, (%rsi), %xmm0, %xmm0 # sched: [6:1.00]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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%1 = insertelement <8 x i16> %a0, i16 %a1, i32 1
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%2 = load i16, i16 *%a2
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%3 = insertelement <8 x i16> %1, i16 %2, i32 3
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ret <8 x i16> %3
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}
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define <4 x i32> @test_pmaddwd(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> *%a2) {
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; GENERIC-LABEL: test_pmaddwd:
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; GENERIC: # BB#0:
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