From 57e74d2010d7c82cb831350968df3a69bbe5a38e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 29 Jul 2014 00:02:40 +0000 Subject: [PATCH] Fix typos / grammar. llvm-svn: 214147 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- llvm/lib/Target/R600/SIInstrInfo.cpp | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 537b80fa8fb1..da15803f2100 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7591,9 +7591,9 @@ static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base, // Return true is there is a nearyby consecutive load to the one provided // (regardless of alignment). We search up and down the chain, looking though -// token factors and other loads (but nothing else). As a result, a true -// results indicates that it is safe to create a new consecutive load adjacent -// to the load provided. +// token factors and other loads (but nothing else). As a result, a true result +// indicates that it is safe to create a new consecutive load adjacent to the +// load provided. static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) { SDValue Chain = LD->getChain(); EVT VT = LD->getMemoryVT(); diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index 4aea68d5c351..872b7cef8597 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -466,7 +466,7 @@ SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI, namespace llvm { namespace AMDGPU { // Helper function generated by tablegen. We are wrapping this with -// an SIInstrInfo function that reutrns bool rather than int. +// an SIInstrInfo function that returns bool rather than int. int isDS(uint16_t Opcode); } }