forked from OSchip/llvm-project
Freeze the reserved registers as soon as isel is complete.
Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
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@ -95,9 +95,6 @@ class MachineRegisterInfo {
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/// started.
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BitVector ReservedRegs;
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/// AllocatableRegs - From TRI->getAllocatableSet.
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mutable BitVector AllocatableRegs;
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/// LiveIns/LiveOuts - Keep track of the physical registers that are
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/// livein/liveout of the function. Live in values are typically arguments in
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/// registers, live out values are typically return values in registers.
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@ -427,6 +424,34 @@ public:
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return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
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}
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/// getReservedRegs - Returns a reference to the frozen set of reserved
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/// registers. This method should always be preferred to calling
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/// TRI::getReservedRegs() when possible.
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const BitVector &getReservedRegs() const {
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assert(reservedRegsFrozen() &&
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"Reserved registers haven't been frozen yet. "
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"Use TRI::getReservedRegs().");
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return ReservedRegs;
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}
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/// isReserved - Returns true when PhysReg is a reserved register.
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///
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/// Reserved registers may belong to an allocatable register class, but the
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/// target has explicitly requested that they are not used.
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///
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bool isReserved(unsigned PhysReg) const {
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return getReservedRegs().test(PhysReg);
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}
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/// isAllocatable - Returns true when PhysReg belongs to an allocatable
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/// register class and it hasn't been reserved.
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///
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/// Allocatable registers may show up in the allocation order of some virtual
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/// register, so a register allocator needs to track its liveness and
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/// availability.
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bool isAllocatable(unsigned PhysReg) const {
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return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
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}
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//===--------------------------------------------------------------------===//
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// LiveIn/LiveOut Management
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@ -306,22 +306,18 @@ void MachineRegisterInfo::dumpUses(unsigned Reg) const {
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void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
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ReservedRegs = TRI->getReservedRegs(MF);
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assert(ReservedRegs.size() == TRI->getNumRegs() &&
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"Invalid ReservedRegs vector from target");
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}
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bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
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const MachineFunction &MF) const {
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assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
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// Check if any overlapping register is modified.
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// Check if any overlapping register is modified, or allocatable so it may be
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// used later.
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for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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if (!def_empty(*AI))
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return false;
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// Check if any overlapping register is allocatable so it may be used later.
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if (AllocatableRegs.empty())
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AllocatableRegs = TRI->getAllocatableSet(MF);
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for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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if (AllocatableRegs.test(*AI))
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if (!def_empty(*AI) || isAllocatable(*AI))
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return false;
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return true;
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}
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@ -474,6 +474,11 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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MRI.replaceRegWith(From, To);
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}
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// Freeze the set of reserved registers now that MachineFrameInfo has been
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// set up. All the information required by getReservedRegs() should be
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// available now.
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MRI.freezeReservedRegs(*MF);
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// Release function-specific state. SDB and CurDAG are already cleared
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// at this point.
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FuncInfo->clear();
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