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[ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions. 

Arm 8.1-M adds a number of related CSEL instructions, including CSINC, CSNEG and CSINV. These choose between two values given the content in CPSR and a condition, performing an increment, negation or inverse of the false value.

This adds some selection for them, either from constant values or patterns. It does not include CSEL directly, which is currently not always making code better. It is still useful, but we will have to check more carefully where it should and shouldn't be used.

Code by Ranjeet Singh and Simon Tatham, with some modifications from me.

Differential revision: https://reviews.llvm.org/D66483

llvm-svn: 370739
This commit is contained in:
David Green 2019-09-03 10:53:07 +00:00
parent a1ae7e3734
commit 57cc65ff47
24 changed files with 2115 additions and 2684 deletions
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6
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -3040,18 +3040,22 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
break;
case ARM::VSELEQD:
case ARM::VSELEQS:
case ARM::VSELEQH:
CC = ARMCC::EQ;
break;
case ARM::VSELGTD:
case ARM::VSELGTS:
case ARM::VSELGTH:
CC = ARMCC::GT;
break;
case ARM::VSELGED:
case ARM::VSELGES:
case ARM::VSELGEH:
CC = ARMCC::GE;
break;
case ARM::VSELVSS:
case ARM::VSELVSD:
case ARM::VSELVSS:
case ARM::VSELVSH:
CC = ARMCC::VS;
break;
}

46
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1634,6 +1634,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::WLS: return "ARMISD::WLS";
case ARMISD::LE: return "ARMISD::LE";
case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
case ARMISD::CSINV: return "ARMISD::CSINV";
case ARMISD::CSNEG: return "ARMISD::CSNEG";
case ARMISD::CSINC: return "ARMISD::CSINC";
}
return nullptr;
}
@ -4815,6 +4818,49 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDValue TrueVal = Op.getOperand(2);
SDValue FalseVal = Op.getOperand(3);
ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
unsigned TVal = CTVal->getZExtValue();
unsigned FVal = CFVal->getZExtValue();
unsigned Opcode = 0;
if (TVal == ~FVal) {
Opcode = ARMISD::CSINV;
} else if (TVal == ~FVal + 1) {
Opcode = ARMISD::CSNEG;
} else if (TVal + 1 == FVal) {
Opcode = ARMISD::CSINC;
} else if (TVal == FVal + 1) {
Opcode = ARMISD::CSINC;
std::swap(TrueVal, FalseVal);
std::swap(TVal, FVal);
CC = ISD::getSetCCInverse(CC, true);
}
if (Opcode) {
// Attempt to use ZR checking TVal is 0, possibly inverting the condition
// to get there. CSINC not is invertable like the other two (~(~a) == a,
// -(-a) == a, but (a+1)+1 != a).
if (FVal == 0 && Opcode != ARMISD::CSINC) {
std::swap(TrueVal, FalseVal);
std::swap(TVal, FVal);
CC = ISD::getSetCCInverse(CC, true);
}
if (TVal == 0)
TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
// Drops F's value because we can get it by inverting/negating TVal.
FalseVal = TrueVal;
SDValue ARMcc;
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
EVT VT = TrueVal.getValueType();
return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
}
}
if (isUnsupportedFloatingType(LHS.getValueType())) {
DAG.getTargetLoweringInfo().softenSetCCOperands(

5
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -240,6 +240,11 @@ class VectorType;
// instructions.
MEMCPY,
// V8.1MMainline condition select
CSINV, // Conditional select invert.
CSNEG, // Conditional select negate.
CSINC, // Conditional select increment.
// Vector load N-element structure to all lanes:
VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
VLD2DUP,

7
llvm/lib/Target/ARM/ARMInstrFormats.td
View File

@ -188,6 +188,13 @@ def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
let DecoderMethod = "DecodeCCOutOperand";
}
// Transform to generate the inverse of a condition code during ISel
def inv_cond_XFORM : SDNodeXForm<imm, [{
ARMCC::CondCodes CC = static_cast<ARMCC::CondCodes>(N->getZExtValue());
return CurDAG->getTargetConstant(ARMCC::getOppositeCondition(CC), SDLoc(N),
MVT::i32);
}]>;
// VPT predicate
def VPTPredNOperand : AsmOperandClass {

10
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -116,6 +116,16 @@ def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>;
def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>;
def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>;
def SDT_ARMCSel : SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCisInt<3>,
SDTCisVT<3, i32>]>;
def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>;
def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>;
def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>;
def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>,
SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,

19
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -5257,6 +5257,25 @@ def t2CSINC : CS<"csinc", 0b1001>;
def t2CSINV : CS<"csinv", 0b1010>;
def t2CSNEG : CS<"csneg", 0b1011>;
let Predicates = [HasV8_1MMainline] in {
def : T2Pat<(ARMcsinc GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
(t2CSINC GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(ARMcsinv GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
(t2CSINV GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(ARMcsneg GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm),
(t2CSNEG GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {
def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval,
(i32 (inv_cond_XFORM imm:$imm)))>;
}
defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;
defm : ModifiedV8_1CSEL<t2CSINV, (xor rGPR:$fval, -1)>;
defm : ModifiedV8_1CSEL<t2CSNEG, (sub 0, rGPR:$fval)>;
}
// CS aliases.
let Predicates = [HasV8_1MMainline] in {

110
llvm/test/CodeGen/Thumb2/csel.ll
View File

@ -6,9 +6,7 @@ define i32 @csinc_const_65(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r1, #6
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinc r0, r1, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -19,11 +17,9 @@ entry:
define i32 @csinc_const_56(i32 %a) {
; CHECK-LABEL: csinc_const_56:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #6
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r1, #5
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinc r0, r1, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -34,11 +30,8 @@ entry:
define i32 @csinc_const_zext(i32 %a) {
; CHECK-LABEL: csinc_const_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r1, #1
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinc r0, zr, zr, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -49,11 +42,9 @@ entry:
define i32 @csinv_const_56(i32 %a) {
; CHECK-LABEL: csinv_const_56:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: mvn r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: mvngt r1, #5
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinv r0, r1, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -64,11 +55,9 @@ entry:
define i32 @csinv_const_65(i32 %a) {
; CHECK-LABEL: csinv_const_65:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: mvn r1, #5
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r1, #5
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinv r0, r1, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -79,11 +68,8 @@ entry:
define i32 @csinv_const_sext(i32 %a) {
; CHECK-LABEL: csinv_const_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinv r0, zr, zr, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -94,11 +80,9 @@ entry:
define i32 @csneg_const(i32 %a) {
; CHECK-LABEL: csneg_const:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: mov.w r1, #-1
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r1, #1
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csneg r0, r1, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -109,11 +93,9 @@ entry:
define i32 @csneg_const_r(i32 %a) {
; CHECK-LABEL: csneg_const_r:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: mov.w r1, #-1
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csneg r0, r1, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -139,9 +121,7 @@ define i32 @csinc_var(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csinc_var:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it le
; CHECK-NEXT: addle r1, r2, #1
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinc r0, r1, r2, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -154,9 +134,7 @@ define i32 @csinc_swap_var(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csinc_swap_var:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: addgt r2, r1, #1
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csinc r0, r2, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -169,9 +147,7 @@ define i32 @csinv_var(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csinv_var:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it le
; CHECK-NEXT: mvnle r1, r2
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csinv r0, r1, r2, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -184,9 +160,7 @@ define i32 @csinv_swap_var(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csinv_swap_var:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: mvngt r2, r1
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csinv r0, r2, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -199,9 +173,7 @@ define i32 @csneg_var(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_var:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it le
; CHECK-NEXT: rsble r1, r2, #0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: csneg r0, r1, r2, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -214,9 +186,7 @@ define i32 @csneg_swap_var_sgt(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_sgt:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: rsbgt r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@ -229,9 +199,7 @@ define i32 @csneg_swap_var_sge(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_sge:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #44
; CHECK-NEXT: it gt
; CHECK-NEXT: rsbgt r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sge i32 %a, 45
@ -244,9 +212,7 @@ define i32 @csneg_swap_var_sle(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_sle:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #46
; CHECK-NEXT: it lt
; CHECK-NEXT: rsblt r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, ge
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sle i32 %a, 45
@ -259,9 +225,7 @@ define i32 @csneg_swap_var_slt(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_slt:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it lt
; CHECK-NEXT: rsblt r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, ge
; CHECK-NEXT: bx lr
entry:
%cmp = icmp slt i32 %a, 45
@ -274,9 +238,7 @@ define i32 @csneg_swap_var_ugt(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_ugt:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it hi
; CHECK-NEXT: rsbhi r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, ls
; CHECK-NEXT: bx lr
entry:
%cmp = icmp ugt i32 %a, 45
@ -289,9 +251,7 @@ define i32 @csneg_swap_var_uge(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_uge:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #44
; CHECK-NEXT: it hi
; CHECK-NEXT: rsbhi r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, ls
; CHECK-NEXT: bx lr
entry:
%cmp = icmp uge i32 %a, 45
@ -304,9 +264,7 @@ define i32 @csneg_swap_var_ule(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_ule:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #46
; CHECK-NEXT: it lo
; CHECK-NEXT: rsblo r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, hs
; CHECK-NEXT: bx lr
entry:
%cmp = icmp ule i32 %a, 45
@ -319,9 +277,7 @@ define i32 @csneg_swap_var_ult(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_ult:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it lo
; CHECK-NEXT: rsblo r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, hs
; CHECK-NEXT: bx lr
entry:
%cmp = icmp ult i32 %a, 45
@ -334,9 +290,7 @@ define i32 @csneg_swap_var_ne(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_ne:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it eq
; CHECK-NEXT: rsbeq r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, ne
; CHECK-NEXT: bx lr
entry:
%cmp = icmp eq i32 %a, 45
@ -349,9 +303,7 @@ define i32 @csneg_swap_var_eq(i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: csneg_swap_var_eq:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: it ne
; CHECK-NEXT: rsbne r2, r1, #0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: csneg r0, r2, r1, eq
; CHECK-NEXT: bx lr
entry:
%cmp = icmp ne i32 %a, 45
@ -364,8 +316,7 @@ define i32 @csinc_inplace(i32 %a, i32 %b) {
; CHECK-LABEL: csinc_inplace:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: addgt r0, #1
; CHECK-NEXT: csinc r0, r0, r0, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %b, 45
@ -378,8 +329,7 @@ define i32 @csinv_inplace(i32 %a, i32 %b) {
; CHECK-LABEL: csinv_inplace:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45
; CHECK-NEXT: it gt
; CHECK-NEXT: mvngt r0, r0
; CHECK-NEXT: csinv r0, r0, r0, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %b, 45

57
llvm/test/CodeGen/Thumb2/mve-abs.ll
View File

@ -40,39 +40,36 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
; CHECK-LABEL: abs_v2i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: vmov r12, s2
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: rsbs.w r3, r12, #0
; CHECK-NEXT: sbc.w lr, r2, r0
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov lr, s4
; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: rsbs.w r3, lr, #0
; CHECK-NEXT: sbc.w r2, r12, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it mi
; CHECK-NEXT: movmi r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq lr, r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: rsbs r5, r4, #0
; CHECK-NEXT: sbc.w r6, r2, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it mi
; CHECK-NEXT: movmi r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csinc r1, zr, zr, pl
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r6, r0
; CHECK-NEXT: moveq r5, r4
; CHECK-NEXT: vmov.32 q0[0], r5
; CHECK-NEXT: vmov.32 q0[1], r6
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: moveq r2, r0
; CHECK-NEXT: moveq r3, lr
; CHECK-NEXT: vmov lr, s6
; CHECK-NEXT: vmov.32 q0[0], r3
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: rsbs.w r2, lr, #0
; CHECK-NEXT: sbc.w r3, r12, r0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r1, zr, zr, pl
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r3, r12
; CHECK-NEXT: vmov.32 q0[2], r3
; CHECK-NEXT: vmov.32 q0[3], lr
; CHECK-NEXT: pop {r4, r5, r6, pc}
; CHECK-NEXT: moveq r2, lr
; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r3, r0
; CHECK-NEXT: vmov.32 q0[3], r3
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = icmp slt <2 x i64> %s1, zeroinitializer
%1 = sub nsw <2 x i64> zeroinitializer, %s1

66
llvm/test/CodeGen/Thumb2/mve-fmath.ll
View File

@ -1326,54 +1326,49 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: ldrb.w r0, [sp, #29]
; CHECK-NEXT: vabs.f16 s4, s0
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: vabs.f16 s8, s1
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: ldrb.w r1, [sp, #25]
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s1
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: tst.w r1, #128
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: ands r1, r1, #128
; CHECK-NEXT: csinc r1, zr, zr, eq
; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #1
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: ldrb.w r0, [sp, #21]
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: ldrb.w r0, [sp, #17]
; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vabs.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2
@ -1381,29 +1376,26 @@ define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x hal
; CHECK-NEXT: ldrb.w r0, [sp, #9]
; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vabs.f16 s8, s3
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: ands r0, r0, #128
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[7], r0

40
llvm/test/CodeGen/Thumb2/mve-minmax.ll
View File

@ -55,15 +55,13 @@ define arm_aapcs_vfpcc <2 x i64> @smin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@ -131,15 +129,13 @@ define arm_aapcs_vfpcc <2 x i64> @umin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@ -208,15 +204,13 @@ define arm_aapcs_vfpcc <2 x i64> @smax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@ -284,15 +278,13 @@ define arm_aapcs_vfpcc <2 x i64> @umax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@ -388,22 +380,20 @@ define arm_aapcs_vfpcc <2 x double> @maxnm_float64_t(<2 x double> %src1, <2 x do
; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: vmov r2, r3, d11
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: vmov r12, r1, d8
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov r2, r3, d10
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r4, zr, zr, eq
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.32 q0[2], r4

70
llvm/test/CodeGen/Thumb2/mve-pred-and.ll
View File

@ -612,18 +612,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q1, q1, q3
@ -650,10 +648,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
@ -662,27 +659,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vand q2, q2, q3
@ -706,10 +700,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: lsrs r2, r2, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: csinc r2, zr, zr, ne
; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov r2, s7
@ -718,27 +711,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vand q2, q3, q2

7
llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
View File

@ -155,11 +155,10 @@ define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: lsrs r1, r1, #5
; CHECK-NEXT: csinc r1, zr, zr, ne
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r1, #1
; CHECK-NEXT: bfi r1, r0, #0, #1

170
llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
View File

@ -6,13 +6,12 @@ define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-LABEL: build_var0_v4i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #0, #4
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #0, #4
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -26,13 +25,12 @@ define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-LABEL: build_var3_v4i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #12, #4
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #12, #4
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -46,16 +44,15 @@ define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a,
; CHECK-LABEL: build_varN_v4i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #0, #4
; CHECK-NEXT: bfi r2, r0, #4, #4
; CHECK-NEXT: bfi r2, r0, #8, #4
; CHECK-NEXT: bfi r2, r0, #12, #4
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #0, #4
; CHECK-NEXT: bfi r1, r0, #4, #4
; CHECK-NEXT: bfi r1, r0, #8, #4
; CHECK-NEXT: bfi r1, r0, #12, #4
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -71,13 +68,12 @@ define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-LABEL: build_var0_v8i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #0, #2
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #0, #2
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -91,13 +87,12 @@ define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-LABEL: build_var3_v8i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #6, #2
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #6, #2
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -111,20 +106,19 @@ define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a,
; CHECK-LABEL: build_varN_v8i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #0, #2
; CHECK-NEXT: bfi r2, r0, #2, #2
; CHECK-NEXT: bfi r2, r0, #4, #2
; CHECK-NEXT: bfi r2, r0, #6, #2
; CHECK-NEXT: bfi r2, r0, #8, #2
; CHECK-NEXT: bfi r2, r0, #10, #2
; CHECK-NEXT: bfi r2, r0, #12, #2
; CHECK-NEXT: bfi r2, r0, #14, #2
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #0, #2
; CHECK-NEXT: bfi r1, r0, #2, #2
; CHECK-NEXT: bfi r1, r0, #4, #2
; CHECK-NEXT: bfi r1, r0, #6, #2
; CHECK-NEXT: bfi r1, r0, #8, #2
; CHECK-NEXT: bfi r1, r0, #10, #2
; CHECK-NEXT: bfi r1, r0, #12, #2
; CHECK-NEXT: bfi r1, r0, #14, #2
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -140,13 +134,12 @@ define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-LABEL: build_var0_v16i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #0, #1
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #0, #1
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -160,13 +153,12 @@ define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-LABEL: build_var3_v16i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #3, #1
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #3, #1
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -180,28 +172,27 @@ define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a,
; CHECK-LABEL: build_varN_v16i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r2, r0, #0, #1
; CHECK-NEXT: bfi r2, r0, #1, #1
; CHECK-NEXT: bfi r2, r0, #2, #1
; CHECK-NEXT: bfi r2, r0, #3, #1
; CHECK-NEXT: bfi r2, r0, #4, #1
; CHECK-NEXT: bfi r2, r0, #5, #1
; CHECK-NEXT: bfi r2, r0, #6, #1
; CHECK-NEXT: bfi r2, r0, #7, #1
; CHECK-NEXT: bfi r2, r0, #8, #1
; CHECK-NEXT: bfi r2, r0, #9, #1
; CHECK-NEXT: bfi r2, r0, #10, #1
; CHECK-NEXT: bfi r2, r0, #11, #1
; CHECK-NEXT: bfi r2, r0, #12, #1
; CHECK-NEXT: bfi r2, r0, #13, #1
; CHECK-NEXT: bfi r2, r0, #14, #1
; CHECK-NEXT: bfi r2, r0, #15, #1
; CHECK-NEXT: vmsr p0, r2
; CHECK-NEXT: bfi r1, r0, #0, #1
; CHECK-NEXT: bfi r1, r0, #1, #1
; CHECK-NEXT: bfi r1, r0, #2, #1
; CHECK-NEXT: bfi r1, r0, #3, #1
; CHECK-NEXT: bfi r1, r0, #4, #1
; CHECK-NEXT: bfi r1, r0, #5, #1
; CHECK-NEXT: bfi r1, r0, #6, #1
; CHECK-NEXT: bfi r1, r0, #7, #1
; CHECK-NEXT: bfi r1, r0, #8, #1
; CHECK-NEXT: bfi r1, r0, #9, #1
; CHECK-NEXT: bfi r1, r0, #10, #1
; CHECK-NEXT: bfi r1, r0, #11, #1
; CHECK-NEXT: bfi r1, r0, #12, #1
; CHECK-NEXT: bfi r1, r0, #13, #1
; CHECK-NEXT: bfi r1, r0, #14, #1
; CHECK-NEXT: bfi r1, r0, #15, #1
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
@ -216,11 +207,10 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var0_v2i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r2, #1
; CHECK-NEXT: rsbs r0, r2, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vldr s10, .LCPI9_0
; CHECK-NEXT: vmov.f32 s9, s8
@ -243,11 +233,10 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var1_v2i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r2, #1
; CHECK-NEXT: rsbs r0, r2, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vldr s8, .LCPI10_0
; CHECK-NEXT: vmov.f32 s9, s8
@ -270,11 +259,10 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_varN_v2i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r2, #1
; CHECK-NEXT: rsbs r0, r2, #0
; CHECK-NEXT: csinc r0, zr, zr, hs
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2

16
llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
View File

@ -57,17 +57,15 @@ define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) {
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: sbcs.w r1, r2, r1
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: bx lr
@ -136,15 +134,13 @@ define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) {
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: sbcs.w r2, r0, r2
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vand q0, q0, q1

14
llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
View File

@ -167,11 +167,10 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-LE-NEXT: vmov r3, s2
; CHECK-LE-NEXT: orrs r1, r2
; CHECK-LE-NEXT: vmov r2, s3
; CHECK-LE-NEXT: clz r1, r1
; CHECK-LE-NEXT: lsrs r1, r1, #5
; CHECK-LE-NEXT: csinc r1, zr, zr, ne
; CHECK-LE-NEXT: orrs r2, r3
; CHECK-LE-NEXT: clz r2, r2
; CHECK-LE-NEXT: lsrs r2, r2, #5
; CHECK-LE-NEXT: csinc r2, zr, zr, ne
; CHECK-LE-NEXT: ands r2, r2, #1
; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
@ -187,11 +186,10 @@ define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-BE-NEXT: vmov r3, s5
; CHECK-BE-NEXT: orrs r1, r2
; CHECK-BE-NEXT: vmov r2, s4
; CHECK-BE-NEXT: clz r1, r1
; CHECK-BE-NEXT: lsrs r1, r1, #5
; CHECK-BE-NEXT: csinc r1, zr, zr, ne
; CHECK-BE-NEXT: orrs r2, r3
; CHECK-BE-NEXT: clz r2, r2
; CHECK-BE-NEXT: lsrs r2, r2, #5
; CHECK-BE-NEXT: csinc r2, zr, zr, ne
; CHECK-BE-NEXT: ands r2, r2, #1
; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r2, r1, #0, #1

28
llvm/test/CodeGen/Thumb2/mve-pred-not.ll
View File

@ -327,18 +327,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vbic q0, q0, q2
@ -359,18 +357,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vbic q0, q0, q2

56
llvm/test/CodeGen/Thumb2/mve-pred-or.ll
View File

@ -425,36 +425,32 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vorr q2, q3, q2
@ -482,10 +478,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
@ -494,27 +489,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vorr q2, q2, q3

56
llvm/test/CodeGen/Thumb2/mve-pred-xor.ll
View File

@ -461,36 +461,32 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: veor q2, q3, q2
@ -518,10 +514,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
@ -530,27 +525,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: veor q2, q2, q3

104
llvm/test/CodeGen/Thumb2/mve-vcmp.ll
View File

@ -378,10 +378,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov r0, s7
@ -389,10 +388,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vbic q0, q3, q4
@ -420,10 +418,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov r0, s7
@ -431,10 +428,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb,
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vbic q0, q3, q4
@ -459,79 +455,67 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov lr, s10
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: subs r1, r0, r2
; CHECK-NEXT: asr.w r12, r0, #31
; CHECK-NEXT: vmov lr, s0
; CHECK-NEXT: subs.w r1, lr, r2
; CHECK-NEXT: asr.w r12, lr, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs.w r2, r1, lr
; CHECK-NEXT: subs r0, r1, r2
; CHECK-NEXT: asr.w r12, r1, #31
; CHECK-NEXT: sbcs.w r2, r12, lr, asr #31
; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r3, #-1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.32 q3[2], r3
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.32 q3[3], r3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vand q1, q5, q4

1256
llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
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File diff suppressed because it is too large Load Diff

1288
llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
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File diff suppressed because it is too large Load Diff

1236
llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
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File diff suppressed because it is too large Load Diff

104
llvm/test/CodeGen/Thumb2/mve-vcmpr.ll
View File

@ -444,10 +444,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: lsrs r2, r2, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: csinc r2, zr, zr, ne
; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s3
@ -455,10 +454,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@ -481,10 +479,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: clz r2, r2
; CHECK-NEXT: lsrs r2, r2, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r2, #-1
; CHECK-NEXT: csinc r2, zr, zr, ne
; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s3
@ -492,10 +489,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@ -521,79 +517,67 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov lr, s10
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: subs r1, r0, r2
; CHECK-NEXT: asr.w r12, r0, #31
; CHECK-NEXT: vmov lr, s0
; CHECK-NEXT: subs.w r1, lr, r2
; CHECK-NEXT: asr.w r12, lr, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: csinv r1, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs.w r2, r1, lr
; CHECK-NEXT: subs r0, r1, r2
; CHECK-NEXT: asr.w r12, r1, #31
; CHECK-NEXT: sbcs.w r2, r12, lr, asr #31
; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r3, #-1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r1, #-1
; CHECK-NEXT: vmov.32 q4[2], r1
; CHECK-NEXT: vmov.32 q3[2], r3
; CHECK-NEXT: vmov.32 q4[3], r1
; CHECK-NEXT: vmov.32 q3[3], r3
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, eq
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vand q1, q5, q4

28
llvm/test/CodeGen/Thumb2/mve-vcmpz.ll
View File

@ -365,18 +365,16 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@ -396,18 +394,16 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: lsrs r0, r0, #5
; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r0, #-1
; CHECK-NEXT: csinc r0, zr, zr, ne
; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3