maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Adjust tablegen includes so we can use Instructions in scheduler models instead of just instregexs. 

This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models.

llvm-svn: 320313
This commit is contained in:
Craig Topper 2017-12-10 17:42:36 +00:00
parent b23e148114
commit 57c2815cbe
2 changed files with 25 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
llvm/lib/Target/X86/X86.td
View File

@ -324,10 +324,34 @@ def FeatureHasFastGather
"Indicates if gather is reasonably fast.">;
//===----------------------------------------------------------------------===//
// X86 processors supported.
// Register File Description
//===----------------------------------------------------------------------===//
include "X86RegisterInfo.td"
include "X86RegisterBanks.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "X86Schedule.td"
include "X86InstrInfo.td"
def X86InstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// X86 processors supported.
//===----------------------------------------------------------------------===//
include "X86ScheduleAtom.td"
include "X86SchedSandyBridge.td"
include "X86SchedHaswell.td"
include "X86SchedBroadwell.td"
include "X86ScheduleSLM.td"
include "X86ScheduleZnver1.td"
include "X86ScheduleBtVer2.td"
include "X86SchedSkylakeClient.td"
include "X86SchedSkylakeServer.td"
def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
"Intel Atom processors">;
@ -954,21 +978,6 @@ def : ProcessorModel<"x86-64", SandyBridgeModel, [
FeatureMacroFusion
]>;
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "X86RegisterInfo.td"
include "X86RegisterBanks.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "X86InstrInfo.td"
def X86InstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// Calling Conventions
//===----------------------------------------------------------------------===//

10
llvm/lib/Target/X86/X86Schedule.td
View File

@ -692,13 +692,3 @@ def GenericPostRAModel : GenericX86Model {
let PostRAScheduler = 1;
}
include "X86ScheduleAtom.td"
include "X86SchedSandyBridge.td"
include "X86SchedHaswell.td"
include "X86SchedBroadwell.td"
include "X86ScheduleSLM.td"
include "X86ScheduleZnver1.td"
include "X86ScheduleBtVer2.td"
include "X86SchedSkylakeClient.td"
include "X86SchedSkylakeServer.td"