forked from OSchip/llvm-project
[AArch64] Generate tbz/tbnz when comparing against zero.
The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
This commit is contained in:
Chad Rosier
parent
087606898b
commit
579c02c9a5
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@ -2916,11 +2916,6 @@ SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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isPowerOf2_64(LHS.getConstantOperandVal(1))) {
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SDValue Test = LHS.getOperand(0);
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uint64_t Mask = LHS.getConstantOperandVal(1);
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// TBZ only operates on i64's, but the ext should be free.
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if (Test.getValueType() == MVT::i32)
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Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
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return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
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DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
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}
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@ -2936,18 +2931,29 @@ SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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isPowerOf2_64(LHS.getConstantOperandVal(1))) {
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SDValue Test = LHS.getOperand(0);
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uint64_t Mask = LHS.getConstantOperandVal(1);
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// TBNZ only operates on i64's, but the ext should be free.
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if (Test.getValueType() == MVT::i32)
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Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
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return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
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DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
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}
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return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
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} else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
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// Don't combine AND since emitComparison converts the AND to an ANDS
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// (a.k.a. TST) and the test in the test bit and branch instruction
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// becomes redundant. This would also increase register pressure.
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uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
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return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
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DAG.getConstant(Mask, MVT::i64), Dest);
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}
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}
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if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
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LHS.getOpcode() != ISD::AND) {
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// Don't combine AND since emitComparison converts the AND to an ANDS
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// (a.k.a. TST) and the test in the test bit and branch instruction
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// becomes redundant. This would also increase register pressure.
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uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
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return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
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DAG.getConstant(Mask, MVT::i64), Dest);
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}
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SDValue CCVal;
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SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
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@ -0,0 +1,258 @@
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; RUN: llc -O1 -march=aarch64 < %s | FileCheck %s
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declare void @t()
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define void @test1(i32 %a) {
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; CHECK-LABEL: @test1
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entry:
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%sub = add nsw i32 %a, -12
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%cmp = icmp slt i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:w[0-9]+]], w0, #12
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; CHECK: tbz [[CMP]], #31
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test2(i64 %a) {
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; CHECK-LABEL: @test2
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entry:
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%sub = add nsw i64 %a, -12
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%cmp = icmp slt i64 %sub, 0
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:x[0-9]+]], x0, #12
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; CHECK: tbz [[CMP]], #63
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test3(i32 %a) {
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; CHECK-LABEL: @test3
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entry:
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%sub = add nsw i32 %a, -12
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%cmp = icmp sgt i32 %sub, -1
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:w[0-9]+]], w0, #12
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; CHECK: tbnz [[CMP]], #31
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test4(i64 %a) {
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; CHECK-LABEL: @test4
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entry:
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%sub = add nsw i64 %a, -12
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%cmp = icmp sgt i64 %sub, -1
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:x[0-9]+]], x0, #12
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; CHECK: tbnz [[CMP]], #63
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test5(i32 %a) {
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; CHECK-LABEL: @test5
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entry:
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%sub = add nsw i32 %a, -12
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%cmp = icmp sge i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:w[0-9]+]], w0, #12
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; CHECK: tbnz [[CMP]], #31
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test6(i64 %a) {
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; CHECK-LABEL: @test6
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entry:
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%sub = add nsw i64 %a, -12
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%cmp = icmp sge i64 %sub, 0
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:x[0-9]+]], x0, #12
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; CHECK: tbnz [[CMP]], #63
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test7(i32 %a) {
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; CHECK-LABEL: @test7
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entry:
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%sub = sub nsw i32 %a, 12
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%cmp = icmp slt i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.end
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; CHECK: sub [[CMP:w[0-9]+]], w0, #12
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; CHECK: tbz [[CMP]], #31
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test8(i64 %val1, i64 %val2, i64 %val3) {
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; CHECK-LABEL: @test8
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%and1 = and i64 %val1, %val2
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%tst1 = icmp slt i64 %and1, 0
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br i1 %tst1, label %if.then1, label %if.end
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; CHECK: tst x0, x1
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; CHECK-NEXT: b.ge .L
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if.then1:
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%and2 = and i64 %val2, %val3
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%tst2 = icmp sge i64 %and2, 0
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br i1 %tst2, label %if.then2, label %if.end
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; CHECK: and [[CMP:x[0-9]+]], x1, x2
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; CHECK-NOT: cmp
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; CHECK: tbnz [[CMP]], #63, .LBB7_5
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if.then2:
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%shifted_op1 = shl i64 %val2, 63
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%shifted_and1 = and i64 %val1, %shifted_op1
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%tst3 = icmp slt i64 %shifted_and1, 0
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br i1 %tst3, label %if.then3, label %if.end
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; CHECK: tst x0, x1, lsl #63
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; CHECK: b.ge .L
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if.then3:
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%shifted_op2 = shl i64 %val2, 62
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%shifted_and2 = and i64 %val1, %shifted_op2
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%tst4 = icmp sge i64 %shifted_and2, 0
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br i1 %tst4, label %if.then4, label %if.end
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; CHECK: tst x0, x1, lsl #62
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; CHECK: b.lt .L
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if.then4:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test9(i64 %val1) {
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; CHECK-LABEL: @test9
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%tst = icmp slt i64 %val1, 0
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br i1 %tst, label %if.then, label %if.end
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; CHECK-NOT: cmp
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; CHECK: tbz x0, #63, .L
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test10(i64 %val1) {
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; CHECK-LABEL: @test10
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%tst = icmp slt i64 %val1, 0
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br i1 %tst, label %if.then, label %if.end
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; CHECK-NOT: cmp
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; CHECK: tbz x0, #63, .L
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test11(i64 %val1, i64* %ptr) {
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; CHECK-LABEL: @test11
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; CHECK: ldr [[CMP:x[0-9]+]], [x1]
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; CHECK-NOT: cmp
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; CHECK: tbz [[CMP]], #63, .L
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%val = load i64* %ptr
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%tst = icmp slt i64 %val, 0
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br i1 %tst, label %if.then, label %if.end
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test12(i64 %val1) {
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; CHECK-LABEL: @test12
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%tst = icmp slt i64 %val1, 0
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br i1 %tst, label %if.then, label %if.end
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; CHECK-NOT: cmp
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; CHECK: tbz x0, #63, .L
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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define void @test13(i64 %val1, i64 %val2) {
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; CHECK-LABEL: @test13
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%or = or i64 %val1, %val2
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%tst = icmp slt i64 %or, 0
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br i1 %tst, label %if.then, label %if.end
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; CHECK: orr [[CMP:x[0-9]+]], x0, x1
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; CHECK-NOT: cmp
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; CHECK: tbz [[CMP]], #63, .L
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if.then:
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call void @t()
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br label %if.end
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if.end:
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ret void
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}
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