From 579168629e04a8d5ab56cbad350aae1a7849ec1b Mon Sep 17 00:00:00 2001
From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Tue, 13 May 2014 11:17:46 +0000
Subject: [PATCH] [mips] Free up two values in SubtargetFeatureFlag by folding
 the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit

Summary:
We are currently very close to the 32-bit limit of the current assembler
implementation. This is because there is no way to represent an instruction
that is available in, for example, Mips3 or Mips32. We have to define a
feature bit that represents this.

This patch cleans up a pair of redundant feature bits and slightly postpones the
point we will reach the limit.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3703

llvm-svn: 208685
---
 llvm/lib/Target/Mips/Mips64InstrInfo.td | 2 +-
 llvm/lib/Target/Mips/MipsInstrInfo.td   | 9 ++++-----
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index 12c6e087c543..df49aa8e7802 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -429,7 +429,7 @@ def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
                     (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
-      Requires<[IsGP64]>;
+      GPR_64;
 def : MipsInstAlias<"daddu $rs, $rt, $imm",
                     (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
                     0>;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 4e375683085c..588cda8b9b60 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -170,10 +170,6 @@ def IsGP32bit    :    Predicate<"!Subtarget.isGP64bit()">,
                       AssemblerPredicate<"!FeatureGP64Bit">;
 def HasMips64    :    Predicate<"Subtarget.hasMips64()">,
                       AssemblerPredicate<"FeatureMips64">;
-def IsGP32       :    Predicate<"!Subtarget.isGP64()">,
-                      AssemblerPredicate<"!FeatureGP64Bit">;
-def IsGP64       :    Predicate<"Subtarget.isGP64()">,
-                      AssemblerPredicate<"FeatureGP64Bit">;
 def HasMips64r2  :    Predicate<"Subtarget.hasMips64r2()">,
                       AssemblerPredicate<"FeatureMips64r2">;
 def HasMips64r6  :    Predicate<"Subtarget.hasMips64r6()">,
@@ -205,6 +201,7 @@ def IsNotNaCl    :    Predicate<"!Subtarget.isTargetNaCl()">;
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 
+class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
 
 //===----------------------------------------------------------------------===//
@@ -1242,7 +1239,9 @@ def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
                     (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
-      Requires<[IsGP32, NotInMicroMips]>;
+      GPR_32 {
+  let AdditionalPredicates = [NotInMicroMips];
+}
 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"addu $rs, $rt, $imm",
                     (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;