forked from OSchip/llvm-project
[Lanai] auto-generate complete test checks; NFC
This file will fail with a common codegen transform that I'm looking at, and I can't tell if that's an improvement or regression based on the sparse checking. llvm-svn: 364684
This commit is contained in:
Sanjay Patel
parent
1242d8f333
commit
573b241c68
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@ -1,10 +1,17 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=lanai | FileCheck %s
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define i32 @f(i32 inreg %a, i32 inreg %b) nounwind ssp {
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entry:
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; CHECK-LABEL: f:
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; CHECK: sub.f %r6, %r7, [[IN:%.*]]
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; CHECK: sel.gt [[IN]], %r0, %rv
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sub.f %r6, %r7, %r3
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; CHECK-NEXT: sel.gt %r3, %r0, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%sub. = select i1 %cmp, i32 %sub, i32 0
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@ -12,10 +19,16 @@ entry:
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}
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define i32 @g(i32 inreg %a, i32 inreg %b) nounwind ssp {
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entry:
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; CHECK-LABEL: g:
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; CHECK: sub.f %r7, %r6, [[IN:%.*]]
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; CHECK: sel.lt [[IN]], %r0, %rv
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sub.f %r7, %r6, %r3
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; CHECK-NEXT: sel.lt %r3, %r0, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%cmp = icmp slt i32 %a, %b
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%sub = sub nsw i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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@ -23,10 +36,16 @@ entry:
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}
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define i32 @h(i32 inreg %a, i32 inreg %b) nounwind ssp {
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entry:
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; CHECK-LABEL: h:
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; CHECK: sub.f %r6, 0x3, [[IN:%.*]]
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; CHECK: sel.gt [[IN]], %r7, %rv
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sub.f %r6, 0x3, %r3
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; CHECK-NEXT: sel.gt %r3, %r7, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%cmp = icmp sgt i32 %a, 3
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%sub = sub nsw i32 %a, 3
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%sub. = select i1 %cmp, i32 %sub, i32 %b
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@ -34,21 +53,39 @@ entry:
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}
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define i32 @i(i32 inreg %a, i32 inreg %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: i:
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; CHECK: sub.f %r7, %r6, [[IN:%.*]]
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; CHECK: sel.ult [[IN]], %r0, %rv
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; CHECK: ! %bb.0:
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sub.f %r7, %r6, %r3
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; CHECK-NEXT: sel.ult %r3, %r0, %rv
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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%cmp = icmp ult i32 %a, %b
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%sub = sub i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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; If SR is live-out, we can't remove cmp if there exists a swapped sub.
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define i32 @j(i32 inreg %a, i32 inreg %b) nounwind {
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entry:
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; CHECK-LABEL: j:
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; CHECK: sub.f %r7, %r6, %r0
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; CHECK: sub %r6, %r7, %rv
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: sub %sp, 0x8, %sp
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; CHECK-NEXT: sub.f %r7, %r6, %r0
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; CHECK-NEXT: bne .LBB4_2
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; CHECK-NEXT: sub %r6, %r7, %rv
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; CHECK-NEXT: .LBB4_1: ! %if.then
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; CHECK-NEXT: sel.gt %rv, %r6, %rv
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; CHECK-NEXT: .LBB4_2: ! %if.else
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; CHECK-NEXT: ld -4[%fp], %pc ! return
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; CHECK-NEXT: add %fp, 0x0, %sp
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; CHECK-NEXT: ld -8[%fp], %fp
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entry:
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%cmp = icmp eq i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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@ -69,10 +106,29 @@ declare void @exit(i32)
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; If the comparison uses the C bit (signed overflow/underflow), we can't
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; omit the comparison.
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define i32 @cmp_ult0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {
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; CHECK-LABEL: cmp_ult0:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: mov hi(t), %r3
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; CHECK-NEXT: or %r3, lo(t), %r3
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; CHECK-NEXT: ld 0[%r3], %r3
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; CHECK-NEXT: sub %r3, 0x11, %r3
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; CHECK-NEXT: sub.f %r3, 0x0, %r0
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; CHECK-NEXT: buge .LBB5_2
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; CHECK-NEXT: sub %sp, 0x10, %sp
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; CHECK-NEXT: .LBB5_1: ! %if.then
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; CHECK-NEXT: add %pc, 0x10, %rca
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; CHECK-NEXT: st %rca, [--%sp]
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; CHECK-NEXT: bt abort
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB5_2: ! %if.else
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; CHECK-NEXT: st %r0, 0[%sp]
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; CHECK-NEXT: add %pc, 0x10, %rca
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; CHECK-NEXT: st %rca, [--%sp]
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; CHECK-NEXT: bt exit
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; CHECK-NEXT: nop
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entry:
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; CHECK-LABEL: cmp_ult0
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; CHECK: sub {{.*}}, 0x11, [[IN:%.*]]
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; CHECK: sub.f [[IN]], 0x0, %r0
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%load = load i32, i32* @t, align 4
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%sub = sub i32 %load, 17
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%cmp = icmp ult i32 %sub, 0
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@ -90,10 +146,29 @@ if.else:
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; Same for the V bit.
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; TODO: add test that exercises V bit individually (VC/VS).
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define i32 @cmp_gt0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {
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; CHECK-LABEL: cmp_gt0:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: st %fp, [--%sp]
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; CHECK-NEXT: add %sp, 0x8, %fp
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; CHECK-NEXT: mov hi(t), %r3
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; CHECK-NEXT: or %r3, lo(t), %r3
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; CHECK-NEXT: ld 0[%r3], %r3
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; CHECK-NEXT: sub %r3, 0x11, %r3
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; CHECK-NEXT: sub.f %r3, 0x1, %r0
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; CHECK-NEXT: blt .LBB6_2
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; CHECK-NEXT: sub %sp, 0x10, %sp
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; CHECK-NEXT: .LBB6_1: ! %if.then
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; CHECK-NEXT: add %pc, 0x10, %rca
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; CHECK-NEXT: st %rca, [--%sp]
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; CHECK-NEXT: bt abort
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB6_2: ! %if.else
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; CHECK-NEXT: st %r0, 0[%sp]
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; CHECK-NEXT: add %pc, 0x10, %rca
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; CHECK-NEXT: st %rca, [--%sp]
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; CHECK-NEXT: bt exit
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; CHECK-NEXT: nop
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entry:
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; CHECK-LABEL: cmp_gt0
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; CHECK: sub {{.*}}, 0x11, [[IN:%.*]]
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; CHECK: sub.f [[IN]], 0x1, %r0
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%load = load i32, i32* @t, align 4
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%sub = sub i32 %load, 17
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%cmp = icmp sgt i32 %sub, 0
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