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[AMDGPU][MC] Enabled constants for src operands of s_cbranch_g_fork 

Fixed bug 32619: https://bugs.llvm.org//show_bug.cgi?id=32619

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D31973

llvm-svn: 300318
This commit is contained in:
Dmitry Preobrazhensky 2017-04-14 11:52:26 +00:00
parent 1022112d77
commit 5714860ee4
3 changed files with 16 additions and 1 deletions
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2
llvm/lib/Target/AMDGPU/SOPInstructions.td
View File

@ -434,7 +434,7 @@ def S_BFE_I64 : SOP2_64_32 <"s_bfe_i64">;
def S_CBRANCH_G_FORK : SOP2_Pseudo <
"s_cbranch_g_fork", (outs),
(ins SReg_64:$src0, SReg_64:$src1),
(ins SCSrc_b64:$src0, SCSrc_b64:$src1),
"$src0, $src1"
> {
let has_sdst = 0;

7
llvm/test/MC/AMDGPU/sop2-err.s Normal file
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@ -0,0 +1,7 @@
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
s_cbranch_g_fork 100, s[6:7]
// GCN: error: invalid operand for instruction
s_cbranch_g_fork s[6:7], 100
// GCN: error: invalid operand for instruction

8
llvm/test/MC/AMDGPU/sop2.s
View File

@ -160,6 +160,14 @@ s_cbranch_g_fork s[4:5], s[6:7]
// SICI: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x95]
// VI: s_cbranch_g_fork s[4:5], s[6:7] ; encoding: [0x04,0x06,0x80,0x94]
s_cbranch_g_fork 1, s[6:7]
// SICI: s_cbranch_g_fork 1, s[6:7] ; encoding: [0x81,0x06,0x80,0x95]
// VI: s_cbranch_g_fork 1, s[6:7] ; encoding: [0x81,0x06,0x80,0x94]
s_cbranch_g_fork s[6:7], 2
// SICI: s_cbranch_g_fork s[6:7], 2 ; encoding: [0x06,0x82,0x80,0x95]
// VI: s_cbranch_g_fork s[6:7], 2 ; encoding: [0x06,0x82,0x80,0x94]
s_absdiff_i32 s2, s4, s6
// SICI: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x96]
// VI: s_absdiff_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x95]