forked from OSchip/llvm-project
[SDAG] reduce code duplication in getNegatedExpression(); NFCI
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7b2442584e
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@ -5695,8 +5695,7 @@ TargetLowering::getNegatibleCost(SDValue Op, SelectionDAG &DAG,
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}
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SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
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bool LegalOperations,
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bool ForCodeSize,
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bool LegalOps, bool OptForSize,
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unsigned Depth) const {
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// fneg is removable even if it has multiple uses.
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if (Op.getOpcode() == ISD::FNEG)
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@ -5704,13 +5703,19 @@ SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
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assert(Depth <= SelectionDAG::MaxRecursionDepth &&
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"getNegatedExpression doesn't match getNegatibleCost");
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const SDNodeFlags Flags = Op->getFlags();
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switch (Op.getOpcode()) {
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// Pre-increment recursion depth for use in recursive calls.
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++Depth;
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const SDNodeFlags Flags = Op->getFlags();
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EVT VT = Op.getValueType();
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unsigned Opcode = Op.getOpcode();
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SDLoc DL(Op);
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switch (Opcode) {
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case ISD::ConstantFP: {
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APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
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V.changeSign();
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return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
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return DAG.getConstantFP(V, DL, VT);
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}
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case ISD::BUILD_VECTOR: {
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SmallVector<SDValue, 4> Ops;
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@ -5721,60 +5726,52 @@ SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
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}
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APFloat V = cast<ConstantFPSDNode>(C)->getValueAPF();
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V.changeSign();
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Ops.push_back(DAG.getConstantFP(V, SDLoc(Op), C.getValueType()));
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Ops.push_back(DAG.getConstantFP(V, DL, C.getValueType()));
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}
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return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Ops);
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return DAG.getBuildVector(VT, DL, Ops);
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}
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case ISD::FADD: {
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SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
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assert((DAG.getTarget().Options.NoSignedZerosFPMath ||
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Flags.hasNoSignedZeros()) &&
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"Expected NSZ fp-flag");
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// fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
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NegatibleCost V0 = getNegatibleCost(Op.getOperand(0), DAG, LegalOperations,
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ForCodeSize, Depth + 1);
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if (V0 != NegatibleCost::Expensive)
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return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
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getNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, ForCodeSize,
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Depth + 1),
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Op.getOperand(1), Flags);
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// fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
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return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
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getNegatedExpression(Op.getOperand(1), DAG,
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LegalOperations, ForCodeSize,
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Depth + 1),
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Op.getOperand(0), Flags);
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// fold (fneg (fadd X, Y)) -> (fsub (fneg X), Y)
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NegatibleCost CostX = getNegatibleCost(X, DAG, LegalOps, OptForSize, Depth);
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if (CostX != NegatibleCost::Expensive)
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return DAG.getNode(
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ISD::FSUB, DL, VT,
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getNegatedExpression(X, DAG, LegalOps, OptForSize, Depth), Y, Flags);
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// fold (fneg (fadd X, Y)) -> (fsub (fneg Y), X)
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return DAG.getNode(
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ISD::FSUB, DL, VT,
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getNegatedExpression(Y, DAG, LegalOps, OptForSize, Depth), X, Flags);
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}
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case ISD::FSUB:
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// fold (fneg (fsub 0, B)) -> B
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if (ConstantFPSDNode *N0CFP =
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isConstOrConstSplatFP(Op.getOperand(0), /*AllowUndefs*/ true))
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if (N0CFP->isZero())
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return Op.getOperand(1);
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// fold (fneg (fsub A, B)) -> (fsub B, A)
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return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
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Op.getOperand(1), Op.getOperand(0), Flags);
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case ISD::FSUB: {
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SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
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// fold (fneg (fsub 0, Y)) -> Y
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if (ConstantFPSDNode *C = isConstOrConstSplatFP(X, /*AllowUndefs*/ true))
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if (C->isZero())
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return Y;
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// fold (fneg (fsub X, Y)) -> (fsub Y, X)
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return DAG.getNode(ISD::FSUB, DL, VT, Y, X, Flags);
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}
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case ISD::FMUL:
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case ISD::FDIV: {
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SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
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// fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
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NegatibleCost V0 = getNegatibleCost(Op.getOperand(0), DAG, LegalOperations,
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ForCodeSize, Depth + 1);
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if (V0 != NegatibleCost::Expensive)
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return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
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getNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, ForCodeSize,
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Depth + 1),
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Op.getOperand(1), Flags);
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NegatibleCost CostX = getNegatibleCost(X, DAG, LegalOps, OptForSize, Depth);
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if (CostX != NegatibleCost::Expensive)
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return DAG.getNode(
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Opcode, DL, VT,
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getNegatedExpression(X, DAG, LegalOps, OptForSize, Depth), Y, Flags);
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// fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
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return DAG.getNode(
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Op.getOpcode(), SDLoc(Op), Op.getValueType(), Op.getOperand(0),
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getNegatedExpression(Op.getOperand(1), DAG, LegalOperations,
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ForCodeSize, Depth + 1),
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Flags);
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Opcode, DL, VT, X,
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getNegatedExpression(Y, DAG, LegalOps, OptForSize, Depth), Flags);
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}
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case ISD::FMA:
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case ISD::FMAD: {
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@ -5782,39 +5779,30 @@ SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
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Flags.hasNoSignedZeros()) &&
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"Expected NSZ fp-flag");
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SDValue Neg2 = getNegatedExpression(Op.getOperand(2), DAG, LegalOperations,
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ForCodeSize, Depth + 1);
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NegatibleCost V0 = getNegatibleCost(Op.getOperand(0), DAG, LegalOperations,
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ForCodeSize, Depth + 1);
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NegatibleCost V1 = getNegatibleCost(Op.getOperand(1), DAG, LegalOperations,
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ForCodeSize, Depth + 1);
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if (V0 > V1) {
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SDValue X = Op.getOperand(0), Y = Op.getOperand(1), Z = Op.getOperand(2);
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SDValue NegZ = getNegatedExpression(Z, DAG, LegalOps, OptForSize, Depth);
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NegatibleCost CostX = getNegatibleCost(X, DAG, LegalOps, OptForSize, Depth);
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NegatibleCost CostY = getNegatibleCost(Y, DAG, LegalOps, OptForSize, Depth);
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if (CostX > CostY) {
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// fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z))
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SDValue Neg0 = getNegatedExpression(
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Op.getOperand(0), DAG, LegalOperations, ForCodeSize, Depth + 1);
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return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), Neg0,
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Op.getOperand(1), Neg2, Flags);
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SDValue NegX = getNegatedExpression(X, DAG, LegalOps, OptForSize, Depth);
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return DAG.getNode(Opcode, DL, VT, NegX, Y, NegZ, Flags);
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}
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// fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z))
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SDValue Neg1 = getNegatedExpression(Op.getOperand(1), DAG, LegalOperations,
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ForCodeSize, Depth + 1);
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return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
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Op.getOperand(0), Neg1, Neg2, Flags);
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SDValue NegY = getNegatedExpression(Y, DAG, LegalOps, OptForSize, Depth);
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return DAG.getNode(Opcode, DL, VT, X, NegY, NegZ, Flags);
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}
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case ISD::FP_EXTEND:
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case ISD::FSIN:
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return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
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getNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, ForCodeSize,
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Depth + 1));
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return DAG.getNode(Opcode, DL, VT,
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getNegatedExpression(Op.getOperand(0), DAG, LegalOps,
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OptForSize, Depth));
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case ISD::FP_ROUND:
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return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
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getNegatedExpression(Op.getOperand(0), DAG,
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LegalOperations, ForCodeSize,
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Depth + 1),
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return DAG.getNode(ISD::FP_ROUND, DL, VT,
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getNegatedExpression(Op.getOperand(0), DAG, LegalOps,
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OptForSize, Depth),
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Op.getOperand(1));
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}
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