forked from OSchip/llvm-project
parent
a2422d8f3e
commit
56d016ab05
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@ -2834,7 +2834,7 @@ bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
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isSrcStr = isMemSrcFromString(Src, Str);
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isSrcStr = isMemSrcFromString(Src, Str);
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bool isSrcConst = isa<ConstantSDNode>(Src);
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bool isSrcConst = isa<ConstantSDNode>(Src);
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bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
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bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
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MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr);
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MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr);
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if (VT != MVT::iAny) {
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if (VT != MVT::iAny) {
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unsigned NewAlign = (unsigned)
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unsigned NewAlign = (unsigned)
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TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
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TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
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@ -3048,8 +3048,8 @@ static SDValue getMemsetStores(SelectionDAG &DAG,
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unsigned VTSize = VT.getSizeInBits() / 8;
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unsigned VTSize = VT.getSizeInBits() / 8;
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SDValue Value = getMemsetValue(Src, VT, DAG);
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SDValue Value = getMemsetValue(Src, VT, DAG);
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SDValue Store = DAG.getStore(Chain, Value,
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SDValue Store = DAG.getStore(Chain, Value,
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getMemBasePlusOffset(Dst, DstOff, DAG),
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getMemBasePlusOffset(Dst, DstOff, DAG),
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DstSV, DstSVOff + DstOff);
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DstSV, DstSVOff + DstOff);
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OutChains.push_back(Store);
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OutChains.push_back(Store);
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DstOff += VTSize;
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DstOff += VTSize;
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}
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}
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