forked from OSchip/llvm-project
[WebAssembly] Add missing SIMD instruction attributes
Summary: These attributes are copied from equivalent instructions in WebAssemblyInstrInfo.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51518 llvm-svn: 342104
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@ -19,13 +19,14 @@ foreach SIZE = [2, 4, 8, 16, 32] in
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def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
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let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in
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defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
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[(set V128:$dst, (vec_t pat))],
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"v128.const\t$dst, "#args,
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"v128.const\t"#args, 0>;
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}
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multiclass SIMDLoad<ValueType vec_t> {
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let mayLoad = 1 in
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let mayLoad = 1, isAsCheapAsAMove = 1 in
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defm LOAD_#vec_t :
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SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
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(outs), (ins P2Align:$align, offset32_op:$off), [],
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@ -33,7 +34,7 @@ multiclass SIMDLoad<ValueType vec_t> {
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"v128.load\t$off$align", 1>;
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}
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multiclass SIMDStore<ValueType vec_t> {
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let mayStore = 1 in
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let mayStore = 1, isAsCheapAsAMove = 1 in
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defm STORE_#vec_t :
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SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
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(outs), (ins P2Align:$align, offset32_op:$off), [],
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