forked from OSchip/llvm-project
[ARM] Expand v1i64 and v2i64 ctpop.
The default is legal, which results in 'Cannot select' errors. This is triggered during selfhost due to a recent cost model change. llvm-svn: 265040
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@ -577,6 +577,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
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setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
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setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
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setOperationAction(ISD::CTPOP, MVT::v1i64, Expand);
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setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
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// NEON does not have single instruction CTTZ for vectors.
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setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
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@ -71,12 +71,28 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
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ret <4 x i32> %tmp2
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}
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define <1 x i64> @vcnt64(<1 x i64>* %A) nounwind {
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; CHECK-LABEL: vcnt64:
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%tmp1 = load <1 x i64>, <1 x i64>* %A
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%tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <2 x i64> @vcntQ64(<2 x i64>* %A) nounwind {
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; CHECK-LABEL: vcntQ64:
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1)
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ret <2 x i64> %tmp2
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}
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declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
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declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone
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declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
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declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone
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declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
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define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vclz8:
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