forked from OSchip/llvm-project
Add support for the -x86-asm-syntax flag, which can be used to choose between
Intel and AT&T style assembly language. The ultimate goal of this is to eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission is not fully operational. llvm-svn: 16639
This commit is contained in:
Chris Lattner
parent
4e59a14909
commit
5683260187
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@ -15,7 +15,8 @@ TARGET = X86
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
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X86GenRegisterInfo.inc X86GenInstrNames.inc \
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X86GenInstrInfo.inc X86GenAsmWriter.inc
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X86GenInstrInfo.inc X86GenATTAsmWriter.inc \
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X86GenIntelAsmWriter.inc
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TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
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$(SourceDir)/../Target.td
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@ -40,10 +41,14 @@ $(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td assembly writer with tblgen"
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$(TARGET)GenATTAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td AT&T assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
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$(TARGET)GenIntelAsmWriter.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td Intel assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -asmwriternum=1 -o $@
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#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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# @echo "Building $(TARGET).td instruction selector with tblgen"
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# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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@ -47,6 +47,18 @@ def X86InstrInfo : InstrInfo {
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16];
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}
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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string AsmWriterClassName = "ATTAsmPrinter";
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int Variant = 0;
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}
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def IntelAsmWriter : AsmWriter {
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string AsmWriterClassName = "IntelAsmPrinter";
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int Variant = 1;
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}
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def X86 : Target {
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// Specify the callee saved registers.
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let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
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@ -56,4 +68,6 @@ def X86 : Target {
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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@ -36,6 +36,16 @@ using namespace llvm;
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namespace {
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Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
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enum AsmWriterFlavor { att, intel };
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cl::opt<AsmWriterFlavor>
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AsmWriterFlavor("x86-asm-syntax",
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumVal(att, " Emit AT&T Style"),
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clEnumVal(intel, " Emit Intel Style"),
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clEnumValEnd),
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cl::init(intel));
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struct GasBugWorkaroundEmitter : public MachineCodeEmitter {
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GasBugWorkaroundEmitter(std::ostream& o)
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@ -67,8 +77,8 @@ namespace {
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bool firstByte;
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};
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struct X86AsmPrinter : public AsmPrinter {
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X86AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) { }
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struct X86IntelAsmPrinter : public AsmPrinter {
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X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) { }
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virtual const char *getPassName() const {
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return "X86 Assembly Printer";
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@ -128,12 +138,17 @@ namespace {
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/// regardless of whether the function is in SSA form.
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///
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FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
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return new X86AsmPrinter(o, tm);
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if (AsmWriterFlavor != intel) {
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std::cerr << "AT&T syntax not fully implemented yet!\n";
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abort();
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}
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return new X86IntelAsmPrinter(o, tm);
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}
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// Include the auto-generated portion of the assembly writer.
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#include "X86GenAsmWriter.inc"
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#include "X86GenIntelAsmWriter.inc"
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/// printConstantPool - Print to the current output stream assembly
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@ -141,7 +156,7 @@ FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
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/// used to print out constants which have been "spilled to memory" by
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/// the code generator.
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///
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void X86AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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void X86IntelAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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const std::vector<Constant*> &CP = MCP->getConstants();
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const TargetData &TD = TM.getTargetData();
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@ -159,7 +174,7 @@ void X86AsmPrinter::printConstantPool(MachineConstantPool *MCP) {
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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setupMachineFunction(MF);
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O << "\n\n";
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@ -207,7 +222,7 @@ static bool isMem(const MachineInstr *MI, unsigned Op) {
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void X86AsmPrinter::printOp(const MachineOperand &MO,
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void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
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bool elideOffsetKeyword /* = false */) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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@ -253,7 +268,7 @@ void X86AsmPrinter::printOp(const MachineOperand &MO,
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}
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}
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void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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if (MI->getOperand(Op).isFrameIndex()) {
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@ -308,7 +323,7 @@ void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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///
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void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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// gas bugs:
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@ -349,7 +364,7 @@ void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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}
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}
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bool X86AsmPrinter::doInitialization(Module &M) {
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bool X86IntelAsmPrinter::doInitialization(Module &M) {
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AsmPrinter::doInitialization(M);
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// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
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//
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@ -375,7 +390,7 @@ static void SwitchSection(std::ostream &OS, std::string &CurSection,
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}
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}
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bool X86AsmPrinter::doFinalization(Module &M) {
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bool X86IntelAsmPrinter::doFinalization(Module &M) {
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const TargetData &TD = TM.getTargetData();
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std::string CurSection;
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