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[ARM][LowOverheadLoops] Use tBcc when reverting 

Check the branch target ranges and use a tBcc instead of t2Bcc when
we can.

Differential Revision: https://reviews.llvm.org/D67796

llvm-svn: 372557
This commit is contained in:
Sam Parker 2019-09-23 08:35:31 +00:00
parent f8e733f149
commit 566127e376
5 changed files with 16 additions and 13 deletions
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19
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
View File

@ -354,8 +354,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
// WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
// beq that branches to the exit branch.
// FIXME: Need to check that we're not trashing the CPSR when generating the
// cmp. We could also try to generate a cbz if the value in LR is also in
// TODO: We could also try to generate a cbz if the value in LR is also in
// another low register.
void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
@ -367,8 +366,11 @@ void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::NoRegister);
// TODO: Try to use tBcc instead
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
ARM::tBcc : ARM::t2Bcc;
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
MIB.add(MI->getOperand(1)); // branch target
MIB.addImm(ARMCC::EQ); // condition code
MIB.addReg(ARM::CPSR);
@ -391,8 +393,6 @@ void ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
}
// Generate a subs, or sub and cmp, and a branch instead of an LE.
// FIXME: Need to check that we're not trashing the CPSR when generating
// the cmp.
void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
@ -405,9 +405,12 @@ void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::NoRegister);
// TODO Try to use tBcc instead.
MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
ARM::tBcc : ARM::t2Bcc;
// Create bne
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
MIB.add(MI->getOperand(1)); // branch target
MIB.addImm(ARMCC::NE); // condition code
MIB.addReg(ARM::CPSR);

2
llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
View File

@ -16,7 +16,7 @@
; CHECK-END: .LBB0_2:
; CHECK-END: sub.w lr, lr, #1
; CHECK-END: cmp.w lr, #0
; CHECK-END: bne.w .LBB0_3
; CHECK-END: bne .LBB0_3
; CHECK-END: b .LBB0_4
; CHECK-END: .LBB0_3:
; CHECK-END: b .LBB0_2

2
llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
View File

@ -4,7 +4,7 @@
# CHECK-NOT: DLS
# CHECK: bb.1.for.body:
# CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
# CHECK: t2Bcc %bb.3, 1, $cpsr
# CHECK: tBcc %bb.3, 1, $cpsr
# CHECK: tB %bb.2, 14, $noreg
# CHECK: bb.2.for.cond.cleanup:
# CHECK: bb.3.for.header:

2
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
View File

@ -3,7 +3,7 @@
# CHECK: bb.5.for.inc16:
# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14
# CHECK: t2CMPri $lr, 0, 14
# CHECK: t2Bcc %bb.6, 1
# CHECK: tBcc %bb.6, 1
# CHECK: tB %bb.2
# CHECK: bb.6.for.cond4.preheader:

4
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
View File

@ -5,11 +5,11 @@
# CHECK: tBcc %bb.2, 3
# CHECK: bb.1.not.preheader:
# CHECK: t2CMPri renamable $lr, 0, 14
# CHECK: t2Bcc %bb.4, 0
# CHECK: tBcc %bb.4, 0
# CHECK: tB %bb.2
# CHECK: bb.3.while.body:
# CHECK: t2CMPri $lr, 0, 14
# CHECK: t2Bcc %bb.3, 1
# CHECK: tBcc %bb.3, 1
# CHECK: tB %bb.4
# CHECK: bb.4.while.end: